SN65LVDS100
- Designed for Signaling Rates ≥ 2 Gbps
- Total Jitter < 65 ps
- Low-Power Alternative for the MC100EP16
- Low 100-ps (Maximum) Part-to-Part Skew
- 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Input Voltage Range - Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels - 3.3-V Supply Operation
- LVDT Integrates 110-Ω Terminating Resistor
- Offered in SOIC and MSOP
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.
The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
技术文档
| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 数据表 | SN65LVDx10x Differential Translator/Repeater 数据表 (Rev. E) | PDF | HTML | 2015年 7月 20日 | ||
| 应用简报 | How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver | 2019年 1月 9日 | ||||
| 应用手册 | Signaling Rate vs. Distance for Differential Buffers | 2010年 1月 26日 | ||||
| 应用手册 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007年 10月 17日 | ||||
| 应用手册 | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 2003年 2月 19日 | ||||
| EVM 用户指南 | 2-GBPS Differential Repeater EVM (Rev. A) | 2002年 11月 11日 | ||||
| 更多文献资料 | HPL EVM Program | 2002年 8月 29日 | ||||
| EVM 用户指南 | 2-GBPS Differential Repeater EVM | 2002年 8月 8日 |
设计和开发
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SN65CML100EVM — SN65CML100 评估模块]]
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SN65LVDS100EVM — SN65LVDS100 评估模块
The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to (...)
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订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
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