SN65LVDS100EVM
SN65LVDS100 评估模块
SN65LVDS100EVM
概述
The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to 50-ohm oscilloscope inputs. Single-ended LVPECL signals can also be applied by using the Vbb reference output voltage provided by either the SN65LVDS100/101 or SN65CML100 devices from TI.
特性
Hardware: SN65LVDS100/101EVM or SN65CML100EVM PWB
- Screw-type SMA jacks serve as the I/O connectors
- Banana jacks serve as the DC power input terminals
Literature:
a) The SN65LVDS100/101EVM or SN65CML100EVM user's guide (SLLU040A) Includes:
- schematic
- board layout
- test results
b) The SN65LVDS100/101 data sheet (SLLS516)
c) Or the SN65CML100 data sheet (SLLS547)
LVDS、M-LVDS 和 PECL IC
技术文档
= TI 精选文档
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| 类型 | 标题 | 下载最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | EVM 用户指南 | 2-GBPS Differential Repeater EVM (Rev. A) | 2002年 11月 11日 | |||
| 证书 | SN65LVDS100EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
| 数据表 | SN65LVDx10x Differential Translator/Repeater 数据表 (Rev. E) | PDF | HTML | 2015年 7月 20日 | |||
| EVM 用户指南 | 2-GBPS Differential Repeater EVM | 2002年 8月 8日 |