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TVP7002

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三通道 8/10 位 165/110MSPS 视频 ADC

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数据表

TVP7002

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数据表 立即订购

米6体育平台手机版_好二三四详情

Type HDMI Companion Rating Catalog Operating temperature range (°C) 0 to 70
Type HDMI Companion Rating Catalog Operating temperature range (°C) 0 to 70
HTQFP (PZP) 100 256 mm² 16 x 16
  • Analog Channels
    • –6-dB to 6-dB Analog Gain
    • Analog Input Multiplexers (MUXs)
    • Automatic Video Clamp
    • Three Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)
    • Clamping: Selectable Clamping Between Bottom Level and Mid Level
    • Offset: 1024-Step Programmable RGB or YPbPr Offset Control
    • Gain: 8-Bit Programmable Gain Control
    • ADC: 8-/10-Bit 165-/110-MSPS ADC
    • Automatic Level Control (ALC) Circuit
    • Composite Sync: Integrated Sync-on-Green Extraction From Green/Luminance Channel
    • Support for DC- and AC-Coupled Input Signals
    • Supports Component Video Standards 480i, 576i, 480p, 576p, 720p, 1080i, and 1080p
    • Supports PC Graphics Inputs up to UXGA Programmable RGB-to-YCbCr Color Space Conversion
  • Horizontal PLL
    • Fully Integrated Horizontal PLL for Pixel Clock Generation
    • 12-MHz to 165-MHz Pixel Clock Generation From HSYNC Input
    • Adjustable Horizontal PLL Loop Bandwidth for Minimum Jitter
    • 5-Bit Programmable Subpixel Accurate Positioning of Sampling Phase
  • Output Formatter
    • Supports 20-bit 4:2:2 Outputs With Embedded Syncs
    • Support for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board Traces
    • Dedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output Data
  • System
    • Industry-Standard Normal/Fast I2C Interface With Register Readback Capability
    • Space-Saving 100-Pin TQFP Package
    • Thermally-Enhanced PowerPAD Package for Better Heat Dissipation
  • Analog Channels
    • –6-dB to 6-dB Analog Gain
    • Analog Input Multiplexers (MUXs)
    • Automatic Video Clamp
    • Three Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)
    • Clamping: Selectable Clamping Between Bottom Level and Mid Level
    • Offset: 1024-Step Programmable RGB or YPbPr Offset Control
    • Gain: 8-Bit Programmable Gain Control
    • ADC: 8-/10-Bit 165-/110-MSPS ADC
    • Automatic Level Control (ALC) Circuit
    • Composite Sync: Integrated Sync-on-Green Extraction From Green/Luminance Channel
    • Support for DC- and AC-Coupled Input Signals
    • Supports Component Video Standards 480i, 576i, 480p, 576p, 720p, 1080i, and 1080p
    • Supports PC Graphics Inputs up to UXGA Programmable RGB-to-YCbCr Color Space Conversion
  • Horizontal PLL
    • Fully Integrated Horizontal PLL for Pixel Clock Generation
    • 12-MHz to 165-MHz Pixel Clock Generation From HSYNC Input
    • Adjustable Horizontal PLL Loop Bandwidth for Minimum Jitter
    • 5-Bit Programmable Subpixel Accurate Positioning of Sampling Phase
  • Output Formatter
    • Supports 20-bit 4:2:2 Outputs With Embedded Syncs
    • Support for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board Traces
    • Dedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output Data
  • System
    • Industry-Standard Normal/Fast I2C Interface With Register Readback Capability
    • Space-Saving 100-Pin TQFP Package
    • Thermally-Enhanced PowerPAD Package for Better Heat Dissipation

The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.

The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.

The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.

All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.

The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.

The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.

The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.

All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.
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类型 标题 下载最新的英语版本 日期
* 数据表 TVP7002 Triple 8/10-Bit 165/110-MSPS Video and Graphics Digitizer With Horiz PLL 数据表 (Rev. C) 2013年 4月 24日
应用手册 TVP7002 PCB Layout Guidelines 2010年 6月 16日

设计和开发

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评估板

TMDXEVM368 — TMS320DM36x 评估模块

TMS320DM36x 数字视频评估模块 (DVEVM) 使开发人员可以立即开始 DaVinci™ 处理器的评估，并开始构建数字视频应用，例如 IP 监控摄像机、数码相框、数字标牌、可视门铃和其它尚未发明的便携式数字视频米6体育平台手机版_好二三四。

数字视频评估模块 (DVEVM) 允许开发人员为 ARM 编写可立即投产的应用程序代码和访问使用达芬奇 API 的 HMJCP 协处理器内核，从而立即开始针对 TMS320DM365 和 TMS320DM368 数字媒体处理器的应用开发。

TMS320DM36x 数字视频评估模块 (DM36x EVM) 包含以下组件：
  • 基于 TMS320DM368 DaVinci™ (...)
用户指南: PDF
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软件编程工具

SLEC023 — TVP7002 Setup Files

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
HDMI、DisplayPort 和 MIPI IC
TVP7002 — 三通道 8/10 位 165/110MSPS 视频 ADC
下载
支持软件

SLEC029 — TVP7002 + THS8200 EVM Kit Setup

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
HDMI、DisplayPort 和 MIPI IC
THS8200 — 三通道 10 位全格式视频 DAC TVP7002 — 三通道 8/10 位 165/110MSPS 视频 ADC TVP70025I — 具有水平 PLL 的三通道 10 位 90MSPS 视频和图形数字转换器
下载
计算工具

SLEC027 — TVP7002, TVP70025i PLL Worksheet

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
HDMI、DisplayPort 和 MIPI IC
TVP7002 — 三通道 8/10 位 165/110MSPS 视频 ADC TVP70025I — 具有水平 PLL 的三通道 10 位 90MSPS 视频和图形数字转换器
下载
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源米6体育平台手机版_好二三四系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短米6体育平台手机版_好二三四上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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模拟工具

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能，允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是米6体育平台手机版_好二三四 (TI) 专有的 DesignSoft 米6体育平台手机版_好二三四。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表 

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用户指南: PDF
英语版 (Rev.A): PDF
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HTQFP (PZP) 100 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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