ZHCSIL6E June   2017  – March 2019 66AK2G12

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  DSS
      2. 4.3.2  DDR EMIF
      3. 4.3.3  GPMC
      4. 4.3.4  Timers
      5. 4.3.5  I2C
      6. 4.3.6  UART
      7. 4.3.7  SPI
      8. 4.3.8  QSPI
      9. 4.3.9  McASP
      10. 4.3.10 USB
      11. 4.3.11 PCIESS
      12. 4.3.12 DCAN
      13. 4.3.13 EMAC
      14. 4.3.14 MLB
      15. 4.3.15 McBSP
      16. 4.3.16 MMC/SD
      17. 4.3.17 GPIO
      18. 4.3.18 ePWM
      19. 4.3.19 PRU-ICSS
      20. 4.3.20 Emulation and Debug Subsystem
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Boot Mode Configuration
        2. 4.3.21.2 Reset
        3. 4.3.21.3 Oscillator Reference Clocks and Clock Generator
        4. 4.3.21.4 Miscellaneous
        5. 4.3.21.5 Interrupt Controllers (INTC)
        6. 4.3.21.6 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On-Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-2  DDR3L SSTL DC Electrical Characteristics
      2. Table 5-3  I2C OPEN DRAIN DC Electrical Characteristics
      3. Table 5-4  Oscillators DC Electrical Characteristics
      4. Table 5-5  LVDS Input Buffer DC Electrical Characteristics
      5. Table 5-6  LVDS Output Buffer DC Electrical Characteristics
      6. Table 5-7  MLB LVDS Buffers DC Electrical Characteristics
      7. Table 5-8  PORn DC Electrical Characteristics
      8. Table 5-9  1.8-Volt I/O LVCMOS DC Electrical Characteristics
      9. Table 5-10 3.3-Volt I/O LVCMOS DC Electrical Characteristics
      10. 5.7.1      USB0_PHY and USB1_PHY DC Electrical Characteristics
      11. 5.7.2      PCIe SERDES DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics for ABY Package
      1. Table 5-11 Thermal Resistance Characteristics for ABY Package
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing
        1. 5.9.1.1 Power-Up Sequence
        2. 5.9.1.2 Power-Down Sequence
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Electrical Data/Timing
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1  Input Clocks / Oscillators
          1. 5.9.3.1.1 System Oscillator (SYSOSC) with External Crystal Circuit
          2. 5.9.3.1.2 System Oscillator (SYSOSC) with External LVCMOS Clock Source
          3. 5.9.3.1.3 System Oscillator (SYSOSC) Not Used
          4. 5.9.3.1.4 Optional LVDS Clock Inputs
        2. 5.9.3.2  Optional LVDS Clock Inputs Not Used
        3. 5.9.3.3  Optional Audio Oscillator (AUDOSC) with External Crystal Circuit
        4. 5.9.3.4  Optional Audio Oscillator (AUDOSC) with External LVCMOS Clock Source
        5. 5.9.3.5  Optional Audio Oscillator (AUDOSC) Not Used
        6. 5.9.3.6  Optional USB PHY Reference Clock
        7. 5.9.3.7  PCIe Reference Clock
        8. 5.9.3.8  Output Clocks
        9. 5.9.3.9  PLLs
          1. 5.9.3.9.1 DDR_PLL Settings
        10. 5.9.3.10 Recommended Clock and Control Signal Transition Behavior
      4. 5.9.4 Peripherals
        1. 5.9.4.1  DCAN
        2. 5.9.4.2  DSS
        3. 5.9.4.3  DDR EMIF
        4. 5.9.4.4  EMAC
          1. 5.9.4.4.1 EMAC MDIO Interface Timings
          2. 5.9.4.4.2 EMAC MII Timings
            1. Table 5-28 Timing Requirements for MII_RXCLK—MII Operation
            2. Table 5-29 Timing Requirements for MII_TXCLK—MII Operation
            3. Table 5-30 Timing Requirements for EMAC MII Receive 10 Mbps and 100 Mbps
            4. Table 5-31 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10 Mbps and 100 Mbps
          3. 5.9.4.4.3 EMAC RMII Timings
            1. Table 5-32 Timing Requirements for EMAC RMII_REFCLK—RMII Operation
            2. Table 5-33 Timing Requirements for EMAC RMII Receive
            3. Table 5-34 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII_REFCLK —RMII Operation
            4. Table 5-35 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 Mbps and 100 Mbps
          4. 5.9.4.4.4 EMAC RGMII Timings
            1. Table 5-36 Timing Requirements for RGMII_RXC—RGMII Operation
            2. Table 5-37 Timing Requirements for EMAC RGMII Input Receive for 10 Mbps, 100 Mbps, and 1000 Mbps
            3. Table 5-38 Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII operation for 10 Mbps, 100 Mbps, and 1000 Mbps
            4. Table 5-39 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII Mode
            5. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode
        5. 5.9.4.5  GPMC
          1. 5.9.4.5.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-41 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-42 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-43 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.4.5.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            2. Table 5-45 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            3. Table 5-46 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        6. 5.9.4.6  I2C
          1. Table 5-47 Timing Requirements for I2C Input Timings
          2. Table 5-48 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        7. 5.9.4.7  McASP
          1. Table 5-49 Timing Requirements for McASP
        8. 5.9.4.8  McBSP
          1. Table 5-51 McBSP Timing Requirements
          2. Table 5-52 McBSP Switching Characteristics
          3. Table 5-53 McBSP Timing Requirements for FSR When GSYNC = 1
        9. 5.9.4.9  MLB
        10. 5.9.4.10 MMC/SD
          1. Table 5-60 MMC Timing Conditions
          2. Table 5-61 Timing Requirements for MMC0_CMD and MMC0_DATn
          3. Table 5-62 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in SDR mode
          4. Table 5-63 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode
          5. Table 5-64 Switching Characteristics for MMCi_CLK
          6. Table 5-65 Switching Characteristics for MMC0_CMD and MMC0_DATn—HSPE=0
          7. Table 5-66 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in SDR mode
          8. Table 5-67 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in DDR mode
        11. 5.9.4.11 PCIESS
        12. 5.9.4.12 PRU-ICSS
          1. 5.9.4.12.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.9.4.12.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-68 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-69 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.9.4.12.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-70 PRU-ICSS PRU Timing Requirements – Parallel Capture Mode
            3. 5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-71 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-72 PRU-ICSS PRU Switching Requirements – Shift Out Mode
          2. 5.9.4.12.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.9.4.12.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-73 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              2. Table 5-74 PRU-ICSS ECAT Timing Requirements – LATCHx_IN
              3. Table 5-75 PRU-ICSS ECAT Switching Requirements – Digital IOs
          3. 5.9.4.12.3 PRU-ICSS MII_RT and Switch
            1. 5.9.4.12.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-76 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-77 PRU-ICSS MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-78 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.4.12.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-79 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-80 PRU-ICSS MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-81 PRU-ICSS MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-82 PRU-ICSS MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
          4. 5.9.4.12.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-83 PRU-ICSS UART Timing Conditions
            2. Table 5-84 Timing Requirements for PRU-ICSS UART Receive
            3. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes
            1. Table 5-86 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            2. Table 5-87 PRU-ICSS PRU Timing Requirements - EnDAT Mode
            3. Table 5-88 PRU-ICSS PRU Switching Requirements - EnDAT Mode
        13. 5.9.4.13 QSPI
        14. 5.9.4.14 SPI
          1. 5.9.4.14.1 SPI—Slave Mode
            1. Table 5-91 Timing Requirements for SPI Input Timings—Slave Mode
            2. Table 5-92 Switching Characteristics for SPI Output Timings—Slave Mode
          2. 5.9.4.14.2 SPI—Master Mode
            1. Table 5-93 SPI Timing Conditions—Master Mode
            2. Table 5-94 Timing Requirements for SPI Input Timings—Master Mode
            3. Table 5-95 Switching Characteristics for SPI Output Timings—Master Mode
        15. 5.9.4.15 Timers
        16. 5.9.4.16 UART
          1. Table 5-98 Timing Requirements for UART
          2. Table 5-99 Switching Characteristics Over Recommended Operating Conditions for UART
        17. 5.9.4.17 USB
      5. 5.9.5 Emulation and Debug Subsystem
        1. 5.9.5.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.5.1.1 JTAG Electrical Data and Timing
            1. Table 5-100 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Arm A15
    4. 6.4  C66x DSP Subsystem
    5. 6.5  C66x Cache Subsystem
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 MSMC
      2. 6.7.2 DDR EMIF
      3. 6.7.3 GPMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MSGMGR
      2. 6.8.2 SEM
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  DCAN
      2. 6.10.2  DSS
      3. 6.10.3  eCAP
      4. 6.10.4  ePWM
      5. 6.10.5  eQEP
      6. 6.10.6  GPIO
      7. 6.10.7  I2C
      8. 6.10.8  ASRC
      9. 6.10.9  McASP
      10. 6.10.10 McBSP
      11. 6.10.11 MLB
      12. 6.10.12 MMC/SD
      13. 6.10.13 NSS
      14. 6.10.14 PCIESS
      15. 6.10.15 QSPI
      16. 6.10.16 SPI
      17. 6.10.17 Timers
      18. 6.10.18 UART
      19. 6.10.19 USB
  7. 7Applications, Implementation, and Layout
    1. 7.1 DDR3L Board Design and Layout Guidelines
      1. 7.1.1 DDR3L General Board Layout Guidelines
      2. 7.1.2 DDR3L Board Design and Layout Guidelines
        1. 7.1.2.1  Board Designs
        2. 7.1.2.2  DDR3L Device Combinations
        3. 7.1.2.3  DDR3L Interface Schematic
          1. 7.1.2.3.1 32-Bit DDR3L Interface
          2. 7.1.2.3.2 16-Bit DDR3L Interface
        4. 7.1.2.4  Compatible JEDEC DDR3L Devices
        5. 7.1.2.5  PCB Stackup
        6. 7.1.2.6  Placement
        7. 7.1.2.7  DDR3L Keepout Region
        8. 7.1.2.8  Bulk Bypass Capacitors
        9. 7.1.2.9  High-Speed Bypass Capacitors
          1. 7.1.2.9.1 Return Current Bypass Capacitors
        10. 7.1.2.10 Net Classes
        11. 7.1.2.11 DDR3L Signal Termination
        12. 7.1.2.12 VREF_DDR Routing
        13. 7.1.2.13 VTT
        14. 7.1.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.1.2.14.1 Four DDR3L Devices
            1. 7.1.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3L Devices
            2. 7.1.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3L Devices
          2. 7.1.2.14.2 One DDR3L Device
            1. 7.1.2.14.2.1 CK and ADDR_CTRL Topologies, One DDR3L Device
            2. 7.1.2.14.2.2 CK and ADDR/CTRL Routing, One DDR3L Device
        15. 7.1.2.15 Data Topologies and Routing Definition
          1. 7.1.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices
          2. 7.1.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices
        16. 7.1.2.16 Routing Specification
          1. 7.1.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 7.1.2.16.2 DQS and DQ Routing Specification
    2. 7.2 High Speed Differential Signal Routing Guidance
    3. 7.3 Power Distribution Network (PDN) Implementation Guidance
      1. 7.3.1 Decoupling/Filtering of Analog Power Supplies and Reference Inputs
        1. 7.3.1.1 PLL Power Supplies
        2. 7.3.1.2 DDR EMIF PHY DLL Power Supplies
        3. 7.3.1.3 DDR EMIF PHY Voltage Reference Input
        4. 7.3.1.4 Internal LDO Outputs
        5. 7.3.1.5 PCIe PHY Power Supply
        6. 7.3.1.6 USB PHY Power Supplies
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
    5. 7.5 Clock Routing Guidelines
      1. 7.5.1 Oscillator Routing
      2. 7.5.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Receiving Notification of Documentation Updates
      1. 8.4.1 静电放电警告
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABY|625
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.2 Pin Attributes

Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball.

Table 4-1 Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14]
C17 AUDOSC_IN AUDOSC_IN 0 I 0 1.8 V DVDD18 Analog
A17 AUDOSC_OUT AUDOSC_OUT 0 O 0 1.8 V DVDD18 Analog
N6 AVDDA_ARMPLL AVDDA_ARMPLL PWR
W20 AVDDA_DDRPLL AVDDA_DDRPLL PWR
N20 AVDDA_DSSPLL AVDDA_DSSPLL PWR
G8 AVDDA_ICSSPLL AVDDA_ICSSPLL PWR
M19 AVDDA_MAINPLL AVDDA_MAINPLL PWR
G14 AVDDA_NSSPLL AVDDA_NSSPLL PWR
G10 AVDDA_UARTPLL AVDDA_UARTPLL PWR
Y3 BOOTCOMPLETE BOOTCOMPLETE 0 OZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD
L21 CPTS_REFCLK_N CPTS_REFCLK_N 0 I 0 1.8 V DVDD18 LVDS
K21 CPTS_REFCLK_P CPTS_REFCLK_P 0 I 0 1.8 V DVDD18 LVDS
J10, J14, J16, K11, K13, K15, K17, K9, L10, L12, L14, L16, L18, M11, M13, M15, M17, M9, N10, N12, N14, N16, P11, P13, P15, P17, P9, R10, R12, R14, R16, R18, R8, T11, T15, T17, T9, U16 CVDD CVDD PWR
J12, M5, N18, N8, T13 CVDD1 CVDD1 PWR
R5 DCAN0_RX DCAN0_RX 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_57 3 IOZ 0
P5 DCAN0_TX DCAN0_TX 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_56 3 IOZ 0
AC13 DDR3_CASn DDR3_CASn 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
Y11 DDR3_CBDQM DDR3_CBDQM 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD12 DDR3_CBDQS_N DDR3_CBDQS_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE12 DDR3_CBDQS_P DDR3_CBDQS_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE13 DDR3_RASn DDR3_RASn 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
Y18 DDR3_RESETn DDR3_RESETn 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL
Y9 DDR3_VREFSSTL DDR3_VREFSSTL 0 A 0 0.5 x DVDD_DDR DVDD_DDR Analog
Y13 DDR3_WEn DDR3_WEn 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AC15 DDR3_A00 DDR3_A00 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
Y15 DDR3_A01 DDR3_A01 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AC16 DDR3_A02 DDR3_A02 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AA15 DDR3_A03 DDR3_A03 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AB16 DDR3_A04 DDR3_A04 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AE17 DDR3_A05 DDR3_A05 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AC14 DDR3_A06 DDR3_A06 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AB15 DDR3_A07 DDR3_A07 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AC17 DDR3_A08 DDR3_A08 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AB17 DDR3_A09 DDR3_A09 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AB14 DDR3_A10 DDR3_A10 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AA16 DDR3_A11 DDR3_A11 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AA17 DDR3_A12 DDR3_A12 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AA12 DDR3_A13 DDR3_A13 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
Y17 DDR3_A14 DDR3_A14 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
Y16 DDR3_A15 DDR3_A15 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AA14 DDR3_BA0 DDR3_BA0 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AB13 DDR3_BA1 DDR3_BA1 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AD17 DDR3_BA2 DDR3_BA2 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AA11 DDR3_CB00 DDR3_CB00 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB11 DDR3_CB01 DDR3_CB01 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC11 DDR3_CB02 DDR3_CB02 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC12 DDR3_CB03 DDR3_CB03 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD13 DDR3_CEn0 DDR3_CEn0 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AB18 DDR3_CKE0 DDR3_CKE0 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
AD15 DDR3_CLKOUT_N0 DDR3_CLKOUT_N0 0 OZ OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD16 DDR3_CLKOUT_N1 DDR3_CLKOUT_N1 0 OZ OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE15 DDR3_CLKOUT_P0 DDR3_CLKOUT_P0 0 OZ OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE16 DDR3_CLKOUT_P1 DDR3_CLKOUT_P1 0 OZ OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD2 DDR3_D00 DDR3_D00 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
Y4 DDR3_D01 DDR3_D01 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC3 DDR3_D02 DDR3_D02 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC2 DDR3_D03 DDR3_D03 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE3 DDR3_D04 DDR3_D04 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA4 DDR3_D05 DDR3_D05 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD3 DDR3_D06 DDR3_D06 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB3 DDR3_D07 DDR3_D07 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA6 DDR3_D08 DDR3_D08 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
Y7 DDR3_D09 DDR3_D09 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
Y6 DDR3_D10 DDR3_D10 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC5 DDR3_D11 DDR3_D11 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB6 DDR3_D12 DDR3_D12 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
Y5 DDR3_D13 DDR3_D13 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC4 DDR3_D14 DDR3_D14 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB5 DDR3_D15 DDR3_D15 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB7 DDR3_D16 DDR3_D16 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB8 DDR3_D17 DDR3_D17 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC7 DDR3_D18 DDR3_D18 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA7 DDR3_D19 DDR3_D19 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA8 DDR3_D20 DDR3_D20 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC6 DDR3_D21 DDR3_D21 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE7 DDR3_D22 DDR3_D22 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD7 DDR3_D23 DDR3_D23 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA10 DDR3_D24 DDR3_D24 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE10 DDR3_D25 DDR3_D25 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD10 DDR3_D26 DDR3_D26 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC10 DDR3_D27 DDR3_D27 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC9 DDR3_D28 DDR3_D28 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB10 DDR3_D29 DDR3_D29 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB9 DDR3_D30 DDR3_D30 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
Y8 DDR3_D31 DDR3_D31 0 IOZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AB4 DDR3_DQM0 DDR3_DQM0 0 OZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA5 DDR3_DQM1 DDR3_DQM1 0 OZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AC8 DDR3_DQM2 DDR3_DQM2 0 OZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA9 DDR3_DQM3 DDR3_DQM3 0 OZ OFF OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE2 DDR3_DQS0_N DDR3_DQS0_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD1 DDR3_DQS0_P DDR3_DQS0_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE4 DDR3_DQS1_N DDR3_DQS1_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD4 DDR3_DQS1_P DDR3_DQS1_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD6 DDR3_DQS2_N DDR3_DQS2_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE6 DDR3_DQS2_P DDR3_DQS2_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AD9 DDR3_DQS3_N DDR3_DQS3_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AE9 DDR3_DQS3_P DDR3_DQS3_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR SSTL PU/PD
AA13 DDR3_ODT0 DDR3_ODT0 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR SSTL PU/PD
W12 DDR3_RZQ0 DDR3_RZQ0 0 A 0 DVDD_DDR Analog
V9 DDR3_RZQ1 DDR3_RZQ1 0 A 0 DVDD_DDR Analog
AD24 DDR_CLK_N DDR_CLK_N 0 I 0 1.8 V DVDD18 LVDS
AE24 DDR_CLK_P DDR_CLK_P 0 I 0 1.8 V DVDD18 LVDS
V22 DSS_DATA0 DSS_DATA0 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A1 1 OZ 0
GPIO0_53 3 IOZ 0
DSS_RFBI_DATA0 5 IOZ 0
U21 DSS_DATA1 DSS_DATA1 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A2 1 OZ 0
eQEP2_S 2 IOZ 0
GPIO0_52 3 IOZ 0
DSS_RFBI_DATA1 5 IOZ 0
W22 DSS_DATA2 DSS_DATA2 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A3 1 OZ 0
eQEP2_I 2 IOZ 0
GPIO0_51 3 IOZ 0
DSS_RFBI_DATA2 5 IOZ 0
MAINPLL_OD_SEL Bootstrap I 0
V23 DSS_DATA3 DSS_DATA3 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A4 1 OZ 0
eQEP2_B 2 I 0
GPIO0_50 3 IOZ 0
DSS_RFBI_DATA3 5 IOZ 0
BOOT_RSVD Bootstrap I 0
U23 DSS_DATA4 DSS_DATA4 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A5 1 OZ 0
eQEP2_A 2 I 0
GPIO0_49 3 IOZ 0
DSS_RFBI_DATA4 5 IOZ 0
NODDR Bootstrap I 0
V24 DSS_DATA5 DSS_DATA5 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A6 1 OZ 0
eQEP1_S 2 IOZ 0
GPIO0_48 3 IOZ 0
DSS_RFBI_DATA5 5 IOZ 0
T21 DSS_DATA6 DSS_DATA6 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A7 1 OZ 0
eQEP1_I 2 IOZ 0
GPIO0_47 3 IOZ 0
EMU19 4 IOZ 0
DSS_RFBI_DATA6 5 IOZ 0
U22 DSS_DATA7 DSS_DATA7 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A8 1 OZ 0
eQEP1_B 2 I 0
GPIO0_46 3 IOZ 0
EMU18 4 IOZ 0
DSS_RFBI_DATA7 5 IOZ 0
T22 DSS_DATA8 DSS_DATA8 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A9 1 OZ 0
eQEP1_A 2 I 0
GPIO0_45 3 IOZ 0
EMU17 4 IOZ 0
DSS_RFBI_DATA8 5 IOZ 0
BOOTMODE15 Bootstrap I 0
R21 DSS_DATA9 DSS_DATA9 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A10 1 OZ 0
eQEP0_S 2 IOZ 0
GPIO0_44 3 IOZ 0
EMU16 4 IOZ 0
DSS_RFBI_DATA9 5 IOZ 0
BOOTMODE14 Bootstrap I 0
U24 DSS_DATA10 DSS_DATA10 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A11 1 OZ 0
eQEP0_I 2 IOZ 0
GPIO0_43 3 IOZ 0
EMU15 4 IOZ 0
DSS_RFBI_DATA10 5 IOZ 0
BOOTMODE13 Bootstrap I 0
V25 DSS_DATA11 DSS_DATA11 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A12 1 OZ 0
eQEP0_B 2 I 0
GPIO0_42 3 IOZ 0
EMU14 4 IOZ 0
DSS_RFBI_DATA11 5 IOZ 0
BOOTMODE12 Bootstrap I 0
T24 DSS_DATA12 DSS_DATA12 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A13 1 OZ 0
eQEP0_A 2 I 0
GPIO0_41 3 IOZ 0
EMU13 4 IOZ 0
DSS_RFBI_DATA12 5 IOZ 0
BOOTMODE11 Bootstrap I 0
P21 DSS_DATA13 DSS_DATA13 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A14 1 OZ 0
eHRPWM_TZn2 2 I 0
GPIO0_40 3 IOZ 0
EMU12 4 IOZ 0
DSS_RFBI_DATA13 5 IOZ 0
BOOTMODE10 Bootstrap I 0
U25 DSS_DATA14 DSS_DATA14 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A15 1 OZ 0
eHRPWM2_B 2 IOZ 0
GPIO0_39 3 IOZ 0
EMU11 4 IOZ 0
DSS_RFBI_DATA14 5 IOZ 0
BOOTMODE09 Bootstrap I 0
R22 DSS_DATA15 DSS_DATA15 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A16 1 OZ 0
eHRPWM2_A 2 IOZ 0
GPIO0_38 3 IOZ 0
EMU10 4 IOZ 0
DSS_RFBI_DATA15 5 IOZ 0
BOOTMODE08 Bootstrap I 0
P23 DSS_DATA16 DSS_DATA16 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A17 1 OZ 0
eHRPWM_TZn1 2 I 0
GPIO0_37 3 IOZ 0
EMU09 4 IOZ 0
DSS_RFBI_CSn0 5 OZ 0
BOOTMODE07 Bootstrap I 0
R24 DSS_DATA17 DSS_DATA17 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A18 1 OZ 0
eHRPWM1_B 2 IOZ 0
GPIO0_36 3 IOZ 0
EMU08 4 IOZ 0
DSS_RFBI_CSn1 5 OZ 0
BOOTMODE06 Bootstrap I 0
N22 DSS_DATA18 DSS_DATA18 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A19 1 OZ 0
eHRPWM1_A 2 IOZ 0
GPIO0_35 3 IOZ 0
EMU07 4 IOZ 0
DSS_RFBI_HSYNC1 5 I 0
BOOTMODE05 Bootstrap I 0
T25 DSS_DATA19 DSS_DATA19 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A20 1 OZ 0
eHRPWM0_SYNCO 2 OZ 0
GPIO0_34 3 IOZ 0
EMU06 4 IOZ 0
DSS_RFBI_TEVSYNC1 5 I 0
BOOTMODE04 Bootstrap I 0
N24 DSS_DATA20 DSS_DATA20 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A21 1 OZ 0
eHRPWM0_SYNCI 2 I 0
GPIO0_33 3 IOZ 0
EMU05 4 IOZ 0
BOOTMODE03 Bootstrap I 0
P24 DSS_DATA21 DSS_DATA21 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A22 1 OZ 0
eHRPWM_TZn0 2 I 0
GPIO0_32 3 IOZ 0
EMU04 4 IOZ 0
BOOTMODE02 Bootstrap I 0
P25 DSS_DATA22 DSS_DATA22 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A23 1 OZ 0
eHRPWM0_B 2 IOZ 0
GPIO0_31 3 IOZ 0
EMU03 4 IOZ 0
BOOTMODE01 Bootstrap I 0
N23 DSS_DATA23 DSS_DATA23 0 OZ OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0
GPMC_A24 1 OZ 0
eHRPWM0_A 2 IOZ 0
GPIO0_30 3 IOZ 0
EMU02 4 IOZ 0
BOOTMODE00 Bootstrap I 0
M25 DSS_DE DSS_DE 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A0 1 OZ 0
PR1_EDIO_OUTVALID 2 OZ 0
GPIO0_57 3 IOZ 0
DSS_RFBI_WEn 5 OZ 0
L25 DSS_FID DSS_FID 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_EDIO_OUTVALID 2 OZ 0
GPIO0_58 3 IOZ 0
DSS_RFBI_A0 5 OZ 0
P22 DSS_HSYNC DSS_HSYNC 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A26 1 OZ 0
PR1_eCAP0_eCAP_SYNCIN 2 I 0
GPIO0_55 3 IOZ 0
DSS_RFBI_HSYNC0 5 I 0
N25 DSS_PCLK DSS_PCLK 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A27 1 OZ 0
PR1_eCAP0_eCAP_SYNCOUT 2 OZ 0
GPIO0_56 3 IOZ 0
DSS_RFBI_REn 5 OZ 0
R25 DSS_VSYNC DSS_VSYNC 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPMC_A25 1 OZ 0
PR1_eCAP0_eCAP_CAPIN_APWM_O 2 IOZ 0
GPIO0_54 3 IOZ 0
DSS_RFBI_TEVSYNC0 5 I 0
F17, F19, G6, H5, J6, K19, L20, L6, M7, U18, U6, V19, W6 DVDD18 DVDD18 PWR
AA23, E23, F11, F15, F21, F7, G12, G16, G20, H11, H13, H15, H9, J20, P19, P7, R20, R6, T19, T23, T7, U20, V21 DVDD33 DVDD33 PWR
G18, H17 DVDD33_USB DVDD33_USB PWR
AD11, AD18, AD5, AE14, AE8, U10, U12, U14, U8, V11, V13, V15, V17, V7, W16, W18 DVDD_DDR DVDD_DDR PWR
W10, W14, W8 DVDD_DDRDLL DVDD_DDRDLL PWR
A23 eHRPWM3_A PR0_EDIO_DATA3 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_73 3 IOZ 0
eHRPWM3_A 4 IOZ 0
B22 eHRPWM3_B PR0_EDIO_DATA2 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_74 3 IOZ 0
eHRPWM3_B 4 IOZ 0
C22 eHRPWM3_SYNCI PR0_EDIO_DATA1 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_75 3 IOZ 0
eHRPWM3_SYNCI 4 I 0
D23 eHRPWM3_SYNCO PR0_EDIO_DATA0 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_76 3 IOZ 0
eHRPWM3_SYNCO 4 OZ 0
M22 EMU00 EMU00 0 IOZ PU OFF 0 3.3 V DVDD33 Yes LVCMOS PU/PD
L22 EMU01 EMU01 0 IOZ PU OFF 0 3.3 V DVDD33 Yes LVCMOS PU/PD
AC21 GPMC_AD0 GPMC_AD0 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_00 3 IOZ 0
AE20 GPMC_AD1 GPMC_AD1 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_01 3 IOZ 0
AD22 GPMC_AD2 GPMC_AD2 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_02 3 IOZ 0
AD20 GPMC_AD3 GPMC_AD3 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_03 3 IOZ 0
AE21 GPMC_AD4 GPMC_AD4 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_04 3 IOZ 0
AE22 GPMC_AD5 GPMC_AD5 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_05 3 IOZ 0
AC20 GPMC_AD6 GPMC_AD6 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_06 3 IOZ 0
AD21 GPMC_AD7 GPMC_AD7 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_07 3 IOZ 0
AE23 GPMC_AD8 GPMC_AD8 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_08 3 IOZ 0
AB20 GPMC_AD9 GPMC_AD9 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_09 3 IOZ 0
AA20 GPMC_AD10 GPMC_AD10 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_10 3 IOZ 0
AD23 GPMC_AD11 GPMC_AD11 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_11 3 IOZ 0
AA21 GPMC_AD12 GPMC_AD12 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_12 3 IOZ 0
AB21 GPMC_AD13 GPMC_AD13 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_13 3 IOZ 0
AB22 GPMC_AD14 GPMC_AD14 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_14 3 IOZ 0
AA22 GPMC_AD15 GPMC_AD15 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_15 3 IOZ 0
AC23 GPMC_ADVn_ALE GPMC_ADVn_ALE 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_17 3 IOZ 0
AC24 GPMC_BEn0_CLE GPMC_BEn0_CLE 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_20 3 IOZ 0
AB24 GPMC_BEn1 GPMC_BEn1 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_21 3 IOZ 0
AB23 GPMC_CLK GPMC_CLK 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_16 3 IOZ 0
AB25 GPMC_CSn0 GPMC_CSn0 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_26 3 IOZ 0
W24 GPMC_CSn1 GPMC_CSn1 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
MLB_DAT 2 IOZ 0
GPIO0_27 3 IOZ 0
W23 GPMC_CSn2 GPMC_CSn2 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
TIMI1 2 I 0
GPIO0_28 3 IOZ 0
Y25 GPMC_CSn3 GPMC_CSn3 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
TIMO1 2 OZ 0
GPIO0_29 3 IOZ 0
AA25 GPMC_DIR GPMC_DIR 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
MLB_SIG 2 IOZ 0
GPIO0_25 3 IOZ 0
AC22 GPMC_OEn_REn GPMC_OEn_REn 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_18 3 IOZ 0
Y24 GPMC_WAIT0 GPMC_WAIT0 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_22 3 IOZ 0
AA24 GPMC_WAIT1 GPMC_WAIT1 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
MLB_CLK 2 I 0
GPIO0_23 3 IOZ 0
Y22 GPMC_WEn GPMC_WEn 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_19 3 IOZ 0
W25 GPMC_WPn GPMC_WPn 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_24 3 IOZ 0
U5 I2C0_SCL I2C0_SCL 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN
W5 I2C0_SDA I2C0_SDA 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN
V6 I2C1_SCL I2C1_SCL 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN
W4 I2C1_SDA I2C1_SDA 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN
V5 I2C2_SCL I2C2_SCL 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN
V4 I2C2_SDA I2C2_SDA 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN
J8, L8 LDO_PCIE_CAP LDO_PCIE_CAP CAP
H19, J18 LDO_USB_CAP LDO_USB_CAP CAP
V2 LRESETn LRESETn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
V1 LRESETNMIENn LRESETNMIENn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
U3 MDIO_CLK MDIO_CLK 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_98 3 IOZ 0
V3 MDIO_DATA MDIO_DATA 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_97 3 IOZ 0
B25 MII_COL MII_COL 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_83 3 IOZ 0
G22 MII_CRS MII_CRS 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RMII_CRS_DV 2 I 0
GPIO0_84 3 IOZ 0
A22 MII_RXCLK MII_RXCLK 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_RXC 1 I 0
GPIO0_72 3 IOZ 0
B24 MII_RXD0 MII_RXD0 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_RXD0 1 I 0
RMII_RXD0 2 I 0
GPIO0_80 3 IOZ 0
C23 MII_RXD1 MII_RXD1 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_RXD1 1 I 0
RMII_RXD1 2 I 0
GPIO0_79 3 IOZ 0
B23 MII_RXD2 MII_RXD2 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_RXD2 1 I 0
GPIO0_78 3 IOZ 0
F22 MII_RXD3 MII_RXD3 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_RXD3 1 I 0
GPIO0_77 3 IOZ 0
A24 MII_RXDV MII_RXDV 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_RXCTL 1 I 0
GPIO0_81 3 IOZ 0
F23 MII_RXER MII_RXER 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RMII_RXER 2 I 0
GPIO0_82 3 IOZ 0
C25 MII_TXCLK MII_TXCLK 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_TXC 1 IOZ 0
GPIO0_85 3 IOZ 0
G23 MII_TXD0 MII_TXD0 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_TXD0 1 OZ 0
RMII_TXD0 2 OZ 0
GPIO0_94 3 IOZ 0
G24 MII_TXD1 MII_TXD1 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_TXD1 1 OZ 0
RMII_TXD1 2 OZ 0
GPIO0_93 3 IOZ 0
G25 MII_TXD2 MII_TXD2 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_TXD2 1 OZ 0
GPIO0_92 3 IOZ 0
D25 MII_TXD3 MII_TXD3 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_TXD3 1 OZ 0
GPIO0_91 3 IOZ 0
H25 MII_TXEN MII_TXEN 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
RGMII_TXCTL 1 OZ 0
RMII_TXEN 2 OZ 0
GPIO0_95 3 IOZ 0
H24 MII_TXER MII_TXER 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_eCAP0_eCAP_SYNCIN 2 I 0
GPIO0_96 3 IOZ 0
eHRPWM_TZn3 4 I 0
L23 MLBP_CLK_N MLBP_CLK_N 0 I 0 1.8 V DVDD18 MLB LVDS
M23 MLBP_CLK_P MLBP_CLK_P 0 I 0 1.8 V DVDD18 MLB LVDS
K22 MLBP_DAT_N MLBP_DAT_N 0 IO 0 1.8 V DVDD18 MLB LVDS
K23 MLBP_DAT_P MLBP_DAT_P 0 IO 0 1.8 V DVDD18 MLB LVDS
M24 MLBP_SIG_N MLBP_SIG_N 0 IO 0 1.8 V DVDD18 MLB LVDS
L24 MLBP_SIG_P MLBP_SIG_P 0 IO 0 1.8 V DVDD18 MLB LVDS
J4 MMC1_CLK MMC1_CLK 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_67 3 IOZ 0
J2 MMC1_CMD MMC1_CMD 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_68 3 IOZ 0
K2 MMC1_POW MMC1_POW 0 OZ PD PD 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_71 3 IOZ 0
J3 MMC1_SDCD MMC1_SDCD 0 I PD PD 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_69 3 IOZ 0
K3 MMC1_SDWP MMC1_SDWP 0 I PD PD 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_70 3 IOZ 0
H3 MMC1_DAT0 MMC1_DAT0 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_66 3 IOZ 0
F5 MMC1_DAT1 MMC1_DAT1 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_65 3 IOZ 0
J5 MMC1_DAT2 MMC1_DAT2 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_64 3 IOZ 0
H4 MMC1_DAT3 MMC1_DAT3 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_63 3 IOZ 0
E3 MMC1_DAT4 MMC1_DAT4 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_62 3 IOZ 0
G4 MMC1_DAT5 MMC1_DAT5 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_61 3 IOZ 0
F4 MMC1_DAT6 MMC1_DAT6 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_60 3 IOZ 0
G5 MMC1_DAT7 MMC1_DAT7 0 IOZ PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD 0
GPIO0_59 3 IOZ 0
W1 NMIn NMIn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
L1 OBSCLK_N OBSCLK_N 0 O 0 1.8 V DVDD18 LVDS
K1 OBSCLK_P OBSCLK_P 0 O 0 1.8 V DVDD18 LVDS
N5 OBSPLL_LOCK OBSPLL_LOCK 0 OZ PD PD 0 1.8 V DVDD18 Yes LVCMOS PU/PD
F2 PCIE_CLK_N PCIE_CLK_N 0 I 0 1.8 V DVDD18 / VDDAHV LVDS
G2 PCIE_CLK_P PCIE_CLK_P 0 I 0 1.8 V DVDD18 / VDDAHV LVDS
H7 PCIE_REFRES PCIE_REFRES 0 A 0 NA n/a Analog
D1 PCIE_RXN0 PCIE_RXN0 0 I 0 DVDD18 / VDDAHV CML
E1 PCIE_RXP0 PCIE_RXP0 0 I 0 DVDD18 / VDDAHV CML
H1 PCIE_TXN0 PCIE_TXN0 0 O 0 DVDD18 / VDDAHV CML
G1 PCIE_TXP0 PCIE_TXP0 0 O 0 DVDD18 / VDDAHV CML
AA3 PORn PORn 0 I 0 3.3 V DVDD33 Yes LVCMOS
A10 PR0_MDIO_DATA PR0_MDIO_DATA 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_04 3 IOZ 0
MCASP0_AXR3 4 IOZ 0
C10 PR0_MDIO_MDCLK PR0_MDIO_MDCLK 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_05 3 IOZ 0
MCASP0_AXR4 4 IOZ 0
E18 PR1_MDIO_DATA PR1_MDIO_DATA 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_46 3 IOZ 0
eCAP0_IN_APWM0_OUT 4 IOZ 0
D18 PR1_MDIO_MDCLK PR1_MDIO_MDCLK 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_47 3 IOZ 0
eCAP1_IN_APWM1_OUT 4 IOZ 0
D3 PR0_PRU0_GPO0 PR0_PRU0_GPO0 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI0 1 I 0
GPIO0_108 3 IOZ 0
MCASP2_AXR0 4 IOZ 0
A2 PR0_PRU0_GPO1 PR0_PRU0_GPO1 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI1 1 I 0
GPIO0_109 3 IOZ 0
MCASP2_AXR1 4 IOZ 0
E4 PR0_PRU0_GPO2 PR0_PRU0_GPO2 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI2 1 I 0
GPIO0_110 3 IOZ 0
MCASP2_AXR2 4 IOZ 0
B1 PR0_PRU0_GPO3 PR0_PRU0_GPO3 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI3 1 I 0
GPIO0_111 3 IOZ 0
MCASP2_AXR3 4 IOZ 0
A3 PR0_PRU0_GPO4 PR0_PRU0_GPO4 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI4 1 I 0
GPIO0_112 3 IOZ 0
MCASP2_AXR4 4 IOZ 0
E5 PR0_PRU0_GPO5 PR0_PRU0_GPO5 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI5 1 I 0
GPIO0_113 3 IOZ 0
MCASP2_AXR5 4 IOZ 0
B2 PR0_PRU0_GPO6 PR0_PRU0_GPO6 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI6 1 I 0
GPIO0_114 3 IOZ 0
MCASP2_ACLKR 4 IOZ 0
D4 PR0_PRU0_GPO7 PR0_PRU0_GPO7 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI7 1 I 0
GPIO0_115 3 IOZ 0
MCASP2_AFSR 4 IOZ 0
E6 PR0_PRU0_GPO8 PR0_PRU0_GPO8 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI8 1 I 0
GPIO0_116 3 IOZ 0
MCASP2_AHCLKR 4 IOZ 0
C2 PR0_PRU0_GPO9 PR0_PRU0_GPO9 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI9 1 I 0
XREFCLK 2 I 0
GPIO0_117 3 IOZ 0
MCASP2_AMUTE 4 IOZ 0
C3 PR0_PRU0_GPO10 PR0_PRU0_GPO10 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI10 1 I 0
GPIO0_118 3 IOZ 0
MCASP2_AFSX 4 IOZ 0
D5 PR0_PRU0_GPO11 PR0_PRU0_GPO11 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI11 1 I 0
GPIO0_119 3 IOZ 0
MCASP2_AHCLKX 4 IOZ 0
B3 PR0_PRU0_GPO12 PR0_PRU0_GPO12 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI12 1 I 0
GPIO0_120 3 IOZ 0
MCASP2_ACLKX 4 IOZ 0
B4 PR0_PRU0_GPO13 PR0_PRU0_GPO13 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI13 1 I 0
GPIO0_121 3 IOZ 0
MCASP1_ACLKR 4 IOZ 0
A4 PR0_PRU0_GPO14 PR0_PRU0_GPO14 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI14 1 I 0
GPIO0_122 3 IOZ 0
MCASP1_AFSR 4 IOZ 0
E7 PR0_PRU0_GPO15 PR0_PRU0_GPO15 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI15 1 I 0
GPIO0_123 3 IOZ 0
MCASP1_AHCLKR 4 IOZ 0
D6 PR0_PRU0_GPO16 PR0_PRU0_GPO16 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI16 1 I 0
GPIO0_124 3 IOZ 0
MCASP1_ACLKX 4 IOZ 0
C4 PR0_PRU0_GPO17 PR0_PRU0_GPO17 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI17 1 I 0
PR1_UART0_RXD 2 I 0
GPIO0_125 3 IOZ 0
MCASP1_AFSX 4 IOZ 0
C5 PR0_PRU0_GPO18 PR0_PRU0_GPO18 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI18 1 I 0
PR0_EDC_LATCH0_IN 2 I 0
GPIO0_126 3 IOZ 0
MCASP1_AHCLKX 4 IOZ 0
A5 PR0_PRU0_GPO19 PR0_PRU0_GPO19 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU0_GPI19 1 I 0
PR0_EDC_SYNC0_OUT 2 OZ 0
GPIO0_127 3 IOZ 0
MCASP1_AMUTE 4 IOZ 0
B5 PR0_PRU1_GPO0 PR0_PRU1_GPO0 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI0 1 I 0
GPIO0_128 3 IOZ 0
MCASP1_AXR0 4 IOZ 0
B6 PR0_PRU1_GPO1 PR0_PRU1_GPO1 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI1 1 I 0
GPIO0_129 3 IOZ 0
MCASP1_AXR1 4 IOZ 0
D7 PR0_PRU1_GPO2 PR0_PRU1_GPO2 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI2 1 I 0
GPIO0_130 3 IOZ 0
MCASP1_AXR2 4 IOZ 0
A6 PR0_PRU1_GPO3 PR0_PRU1_GPO3 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI3 1 I 0
GPIO0_131 3 IOZ 0
MCASP1_AXR3 4 IOZ 0
C6 PR0_PRU1_GPO4 PR0_PRU1_GPO4 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI4 1 I 0
GPIO0_132 3 IOZ 0
MCASP1_AXR4 4 IOZ 0
E8 PR0_PRU1_GPO5 PR0_PRU1_GPO5 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI5 1 I 0
GPIO0_133 3 IOZ 0
MCASP1_AXR5 4 IOZ 0
A7 PR0_PRU1_GPO6 PR0_PRU1_GPO6 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI6 1 I 0
GPIO0_134 3 IOZ 0
MCASP1_AXR6 4 IOZ 0
D8 PR0_PRU1_GPO7 PR0_PRU1_GPO7 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI7 1 I 0
GPIO0_135 3 IOZ 0
MCASP1_AXR7 4 IOZ 0
F9 PR0_PRU1_GPO8 PR0_PRU1_GPO8 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI8 1 I 0
GPIO0_136 3 IOZ 0
MCASP1_AXR8 4 IOZ 0
B7 PR0_PRU1_GPO9 PR0_PRU1_GPO9 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI9 1 I 0
GPIO0_137 3 IOZ 0
MCASP1_AXR9 4 IOZ 0
C7 PR0_PRU1_GPO10 PR0_PRU1_GPO10 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI10 1 I 0
GPIO0_138 3 IOZ 0
MCASP0_AMUTE 4 IOZ 0
E9 PR0_PRU1_GPO11 PR0_PRU1_GPO11 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI11 1 I 0
GPIO0_139 3 IOZ 0
MCASP0_ACLKR 4 IOZ 0
A8 PR0_PRU1_GPO12 PR0_PRU1_GPO12 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI12 1 I 0
GPIO0_140 3 IOZ 0
MCASP0_AFSR 4 IOZ 0
B8 PR0_PRU1_GPO13 PR0_PRU1_GPO13 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI13 1 I 0
GPIO0_141 3 IOZ 0
MCASP0_AHCLKR 4 IOZ 0
D9 PR0_PRU1_GPO14 PR0_PRU1_GPO14 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI14 1 I 0
GPIO0_142 3 IOZ 0
MCASP0_ACLKX 4 IOZ 0
C8 PR0_PRU1_GPO15 PR0_PRU1_GPO15 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI15 1 I 0
GPIO0_143 3 IOZ 0
MCASP0_AFSX 4 IOZ 0
C9 PR0_PRU1_GPO16 PR0_PRU1_GPO16 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI16 1 I 0
GPIO1_00 3 IOZ 0
MCASP0_AHCLKX 4 IOZ 0
B9 PR0_PRU1_GPO17 PR0_PRU1_GPO17 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI17 1 I 0
PR1_UART0_TXD 2 OZ 0
GPIO1_01 3 IOZ 0
MCASP0_AXR0 4 IOZ 0
A9 PR0_PRU1_GPO18 PR0_PRU1_GPO18 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI18 1 I 0
PR0_EDC_LATCH1_IN 2 I 0
GPIO1_02 3 IOZ 0
MCASP0_AXR1 4 IOZ 0
B10 PR0_PRU1_GPO19 PR0_PRU1_GPO19 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_PRU1_GPI19 1 I 0
PR0_EDC_SYNC1_OUT 2 OZ 0
GPIO1_03 3 IOZ 0
MCASP0_AXR2 4 IOZ 0
E10 PR1_PRU0_GPO0 PR1_PRU0_GPO0 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI0 1 I 0
GPIO1_06 3 IOZ 0
MCASP0_AXR5 4 IOZ 0
D10 PR1_PRU0_GPO1 PR1_PRU0_GPO1 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI1 1 I 0
GPIO1_07 3 IOZ 0
MCASP0_AXR6 4 IOZ 0
F10 PR1_PRU0_GPO2 PR1_PRU0_GPO2 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI2 1 I 0
GPIO1_08 3 IOZ 0
MCASP0_AXR7 4 IOZ 0
C11 PR1_PRU0_GPO3 PR1_PRU0_GPO3 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI3 1 I 0
GPIO1_09 3 IOZ 0
MCASP0_AXR8 4 IOZ 0
D11 PR1_PRU0_GPO4 PR1_PRU0_GPO4 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI4 1 I 0
MMC0_POW 2 OZ 0
GPIO1_10 3 IOZ 0
MCASP0_AXR9 4 IOZ 0
E11 PR1_PRU0_GPO5 PR1_PRU0_GPO5 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI5 1 I 0
MMC0_SDWP 2 I 0
GPIO1_11 3 IOZ 0
MCASP0_AXR10 4 IOZ 0
F12 PR1_PRU0_GPO6 PR1_PRU0_GPO6 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI6 1 I 0
MMC0_SDCD 2 I 0
GPIO1_12 3 IOZ 0
MCASP0_AXR11 4 IOZ 0
E12 PR1_PRU0_GPO7 PR1_PRU0_GPO7 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI7 1 I 0
MMC0_DAT7 2 IOZ 0
GPIO1_13 3 IOZ 0
MCASP0_AXR12 4 IOZ 0
C12 PR1_PRU0_GPO8 PR1_PRU0_GPO8 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI8 1 I 0
MMC0_DAT6 2 IOZ 0
GPIO1_14 3 IOZ 0
MCASP0_AXR13 4 IOZ 0
B11 PR1_PRU0_GPO9 PR1_PRU0_GPO9 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI9 1 I 0
MMC0_DAT5 2 IOZ 0
GPIO1_15 3 IOZ 0
MCASP0_AXR14 4 IOZ 0
B12 PR1_PRU0_GPO10 PR1_PRU0_GPO10 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI10 1 I 0
MMC0_DAT4 2 IOZ 0
GPIO1_16 3 IOZ 0
MCASP0_AXR15 4 IOZ 0
A12 PR1_PRU0_GPO11 PR1_PRU0_GPO11 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI11 1 I 0
MMC0_DAT3 2 IOZ 0
GPIO1_17 3 IOZ 0
A11 PR1_PRU0_GPO12 PR1_PRU0_GPO12 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI12 1 I 0
MMC0_DAT2 2 IOZ 0
GPIO1_18 3 IOZ 0
A13 PR1_PRU0_GPO13 PR1_PRU0_GPO13 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI13 1 I 0
MMC0_DAT1 2 IOZ 0
GPIO1_19 3 IOZ 0
B13 PR1_PRU0_GPO14 PR1_PRU0_GPO14 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI14 1 I 0
MMC0_DAT0 2 IOZ 0
GPIO1_20 3 IOZ 0
F13 PR1_PRU0_GPO15 PR1_PRU0_GPO15 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI15 1 I 0
MMC0_CLK 2 IOZ 0
GPIO1_21 3 IOZ 0
C13 PR1_PRU0_GPO16 PR1_PRU0_GPO16 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI16 1 I 0
MMC0_CMD 2 IOZ 0
GPIO1_22 3 IOZ 0
E13 PR1_PRU0_GPO17 PR1_PRU0_GPO17 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI17 1 I 0
GPIO1_23 3 IOZ 0
eHRPWM_TZn4 4 I 0
eHRPWM_SOCA 5 OZ 0
D12 PR1_PRU0_GPO18 PR1_PRU0_GPO18 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI18 1 I 0
PR1_EDC_LATCH0_IN 2 I 0
GPIO1_24 3 IOZ 0
eHRPWM4_A 4 IOZ 0
D13 PR1_PRU0_GPO19 PR1_PRU0_GPO19 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU0_GPI19 1 I 0
PR1_EDC_SYNC0_OUT 2 OZ 0
GPIO1_25 3 IOZ 0
eHRPWM4_B 4 IOZ 0
A14 PR1_PRU1_GPO0 PR1_PRU1_GPO0 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI0 1 I 0
GPIO1_26 3 IOZ 0
B14 PR1_PRU1_GPO1 PR1_PRU1_GPO1 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI1 1 I 0
GPIO1_27 3 IOZ 0
C14 PR1_PRU1_GPO2 PR1_PRU1_GPO2 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI2 1 I 0
GPIO1_28 3 IOZ 0
E14 PR1_PRU1_GPO3 PR1_PRU1_GPO3 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI3 1 I 0
GPIO1_29 3 IOZ 0
D14 PR1_PRU1_GPO4 PR1_PRU1_GPO4 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI4 1 I 0
GPIO1_30 3 IOZ 0
A15 PR1_PRU1_GPO5 PR1_PRU1_GPO5 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI5 1 I 0
GPIO1_31 3 IOZ 0
F14 PR1_PRU1_GPO6 PR1_PRU1_GPO6 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI6 1 I 0
GPIO1_32 3 IOZ 0
B15 PR1_PRU1_GPO7 PR1_PRU1_GPO7 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI7 1 I 0
GPIO1_33 3 IOZ 0
C15 PR1_PRU1_GPO8 PR1_PRU1_GPO8 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI8 1 I 0
GPIO1_34 3 IOZ 0
D15 PR1_PRU1_GPO9 PR1_PRU1_GPO9 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI9 1 I 0
MCBSP_DR 2 I 0
GPIO1_35 3 IOZ 0
A16 PR1_PRU1_GPO10 PR1_PRU1_GPO10 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI10 1 I 0
MCBSP_DX 2 OZ 0
GPIO1_36 3 IOZ 0
E15 PR1_PRU1_GPO11 PR1_PRU1_GPO11 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI11 1 I 0
MCBSP_FSX 2 IOZ 0
GPIO1_37 3 IOZ 0
B16 PR1_PRU1_GPO12 PR1_PRU1_GPO12 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI12 1 I 0
MCBSP_CLKX 2 IOZ 0
GPIO1_38 3 IOZ 0
C16 PR1_PRU1_GPO13 PR1_PRU1_GPO13 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI13 1 I 0
MCBSP_FSR 2 IOZ 0
GPIO1_39 3 IOZ 0
D17 PR1_PRU1_GPO14 PR1_PRU1_GPO14 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI14 1 I 0
MCBSP_CLKR 2 IOZ 0
GPIO1_40 3 IOZ 0
C18 PR1_PRU1_GPO15 PR1_PRU1_GPO15 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI15 1 I 0
GPIO1_41 3 IOZ 0
D16 PR1_PRU1_GPO16 PR1_PRU1_GPO16 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI16 1 I 0
GPIO1_42 3 IOZ 0
F16 PR1_PRU1_GPO17 PR1_PRU1_GPO17 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI17 1 I 0
GPIO1_43 3 IOZ 0
eHRPWM_TZn5 4 I 0
eHRPWM_SOCB 5 OZ 0
E17 PR1_PRU1_GPO18 PR1_PRU1_GPO18 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI18 1 I 0
PR1_EDC_LATCH1_IN 2 I 0
GPIO1_44 3 IOZ 0
eHRPWM5_A 4 IOZ 0
E16 PR1_PRU1_GPO19 PR1_PRU1_GPO19 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_PRU1_GPI19 1 I 0
PR1_EDC_SYNC1_OUT 2 OZ 0
GPIO1_45 3 IOZ 0
eHRPWM5_B 4 IOZ 0
K25 QSPI_CLK QSPI_CLK 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_58 3 IOZ 0
J25 QSPI_CSn0 QSPI_CSn0 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_64 3 IOZ 0
H23 QSPI_CSn1 QSPI_CSn1 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
CLKOUT 1 OZ 0
GPIO1_65 3 IOZ 0
H22 QSPI_CSn2 QSPI_CSn2 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
DCAN1_TX 1 OZ 0
PR1_UART0_CTSN 2 I 0
GPIO1_66 3 IOZ 0
USB0_EXT_TRIGGER 4 I 0
H21 QSPI_CSn3 QSPI_CSn3 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 1
DCAN1_RX 1 I 1
PR1_UART0_RTSN 2 OZ 1
GPIO1_67 3 IOZ 1
USB1_EXT_TRIGGER 4 I 1
J23 QSPI_D0 QSPI_D0 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_60 3 IOZ 0
J22 QSPI_D1 QSPI_D1 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_61 3 IOZ 0
J21 QSPI_D2 QSPI_D2 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_62 3 IOZ 0
J24 QSPI_D3 QSPI_D3 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_63 3 IOZ 0
K24 QSPI_RCLK QSPI_RCLK 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_59 3 IOZ 0
W2 RESETFULLn RESETFULLn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
W3 RESETn RESETn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
Y2 RESETSTATn RESETSTATn 0 O DRIVE 0 (OFF) DRIVE 0 (OFF) 0 3.3 V DVDD33 Yes LVCMOS
D24 RMII_REFCLK RMII_REFCLK 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_eCAP0_eCAP_SYNCOUT 2 OZ 0
M2 SPI0_CLK SPI0_CLK 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
N4 SPI0_SIMO SPI0_SIMO 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
M1 SPI0_SOMI SPI0_SOMI 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
N2 SPI1_CLK SPI1_CLK 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
P2 SPI1_SIMO SPI1_SIMO 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
N1 SPI1_SOMI SPI1_SOMI 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
R2 SPI2_CLK SPI2_CLK 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_103 3 IOZ 0
R3 SPI2_SIMO SPI2_SIMO 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_105 3 IOZ 0
R4 SPI2_SOMI SPI2_SOMI 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_104 3 IOZ 0
E24 SPI3_CLK SPI3_CLK 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_UART0_TXD 2 OZ 0
GPIO0_88 3 IOZ 0
F24 SPI3_SIMO SPI3_SIMO 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_UART0_RTSN 2 OZ 0
GPIO0_90 3 IOZ 0
F25 SPI3_SOMI SPI3_SOMI 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR0_UART0_CTSN 2 I 0
GPIO0_89 3 IOZ 0
M3 SPI0_SCSn0 SPI0_SCSn0 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 1
M4 SPI0_SCSn1 SPI0_SCSn1 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_99 3 IOZ 0
P1 SPI1_SCSn0 SPI1_SCSn0 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 1
N3 SPI1_SCSn1 SPI1_SCSn1 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_100 3 IOZ 0
P3 SPI2_SCSn0 SPI2_SCSn0 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_101 3 IOZ 0
P4 SPI2_SCSn1 SPI2_SCSn1 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO0_102 3 IOZ 0
C24 SPI3_SCSn0 SPI3_SCSn0 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 1
PR0_eCAP0_eCAP_CAPIN_APWM_O 2 IOZ 1
GPIO0_86 3 IOZ 1
E25 SPI3_SCSn1 SPI3_SCSn1 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 1
PR0_UART0_RXD 2 I 1
GPIO0_87 3 IOZ 1
M21 SYSCLKOUT SYSCLKOUT 0 OZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD
R1 SYSCLKSEL SYSCLKSEL 0 I 0 3.3 V DVDD33 Yes LVCMOS
AC25 SYSCLK_N SYSCLK_N 0 I 0 1.8 V DVDD18 LVDS
AD25 SYSCLK_P SYSCLK_P 0 I 0 1.8 V DVDD18 LVDS
AC19 SYSOSC_IN SYSOSC_IN 0 I 0 1.8 V DVDD18 Analog
AE19 SYSOSC_OUT SYSOSC_OUT 0 O 0 1.8 V DVDD18 Analog
L3 TCK TCK 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
L5 TDI TDI 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
K5 TDO TDO 0 OZ PU OFF 0 3.3 V DVDD33 LVCMOS PU/PD
K4 TMS TMS 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
L4 TRSTn TRSTn 0 I PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD
T2 UART0_CTSn UART0_CTSn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
TIMI0 1 I 0
GPIO0_106 3 IOZ 0
U1 UART0_RTSn UART0_RTSn 0 OZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0
TIMO0 1 OZ 0
GPIO0_107 3 IOZ 0
T4 UART0_RXD UART0_RXD 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 1
T1 UART0_TXD UART0_TXD 0 OZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD
U2 UART1_CTSn UART1_CTSn 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_50 3 IOZ 0
U4 UART1_RTSn UART1_RTSn 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_51 3 IOZ 0
T3 UART1_RXD UART1_RXD 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_48 3 IOZ 0
T5 UART1_TXD UART1_TXD 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
GPIO1_49 3 IOZ 0
D22 UART2_CTSn UART2_CTSn 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_EDIO_DATA1 1 IOZ 0
UART0_DTRn 2 OZ 0
GPIO1_54 3 IOZ 0
CPTS_TS_SYNC 4 OZ 0
C21 UART2_RTSn UART2_RTSn 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_EDIO_DATA0 1 IOZ 0
UART0_RIN 2 I 0
GPIO1_55 3 IOZ 0
CPTS_TS_COMP 4 OZ 0
E21 UART2_RXD UART2_RXD 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_EDIO_DATA3 1 IOZ 0
UART0_DCDn 2 I 0
GPIO1_52 3 IOZ 0
CPTS_HW1_TSPUSH 4 I 0
D21 UART2_TXD UART2_TXD 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0
PR1_EDIO_DATA2 1 IOZ 0
UART0_DSRn 2 I 0
GPIO1_53 3 IOZ 0
CPTS_HW2_TSPUSH 4 I 0
B18 USB0_DM USB0_DM 0 IO 0 DVDD18 / DVDD33_USB USB0_PHY
A18 USB0_DP USB0_DP 0 IO 0 DVDD18 / DVDD33_USB USB0_PHY
E19 USB0_DRVVBUS USB0_DRVVBUS 0 OZ PD PD 0 3.3 V DVDD33_USB Yes LVCMOS PU/PD
A19 USB0_ID USB0_ID 0 A 0 DVDD18 / DVDD33_USB USB0_PHY
C19 USB0_TXRTUNE_RKELVIN USB0_TXRTUNE_RKELVIN 0 A DVDD18 / DVDD33_USB USB0_PHY
B19 USB0_VBUS USB0_VBUS 0 A 0 5.0 V n/a - Fail-safe USB0_PHY
D19 USB0_XO USB0_XO 0 I 0 1.8 V DVDD18 / DVDD33_USB USB0_PHY
A20 USB1_DM USB1_DM 0 IO 0 DVDD18 / DVDD33_USB USB1_PHY
B20 USB1_DP USB1_DP 0 IO 0 DVDD18 / DVDD33_USB USB1_PHY
B21 USB1_DRVVBUS USB1_DRVVBUS 0 OZ PD PD 0 3.3 V DVDD33_USB Yes LVCMOS PU/PD
E20 USB1_ID USB1_ID 0 A 0 DVDD18 / DVDD33_USB USB1_PHY
D20 USB1_TXRTUNE_RKELVIN USB1_TXRTUNE_RKELVIN 0 A DVDD18 / DVDD33_USB USB1_PHY
A21 USB1_VBUS USB1_VBUS 0 A 0 5.0 V n/a - Fail-safe USB1_PHY
C20 USB1_XO USB1_XO 0 I 0 1.8 V DVDD18 / DVDD33_USB USB1_PHY
K7 VDDAHV VDDAHV PWR
Y21 VPP VPP PWR
W21 VPP2 VPP2 PWR
A1, A25, AD14, AD8, AE1, AE11, AE18, AE25, AE5, C1, E2, E22, F1, F20, F3, F6, F8, G11, G13, G15, G17, G19, G21, G7, G9, H10, H12, H14, H16, H18, H20, H6, H8, J1, J11, J13, J15, J17, J19, J7, J9, K10, K12, K14, K16, K18, K20, K6, K8, L11, L13, L15, L17, L19, L7, L9, M10, M12, M14, M16, M18, M20, M6, M8, N11, N13, N15, N17, N19, N21, N7, N9, P10, P12, P14, P16, P18, P20, P6, P8, R11, R13, R15, R17, R19, R23, R7, R9, T10, T12, T14, T16, T18, T20, T6, T8, U11, U13, U15, U17, U19, U7, U9, V10, V12, V14, V16, V18, V20, V8, W11, W13, W15, W17, W7, W9, Y10, Y23 VSS VSS GND
B17 VSS_OSC_AUDIO VSS_OSC_AUDIO GND
AD19 VSS_OSC_SYS VSS_OSC_SYS GND

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

    4. NOTE

    Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions.

    Table 4-1, Pin Attributes only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Refer to the respective peripheral chapter of the Device TRM for information associated with peripheral signal multiplexing.

  4. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.

      2. NOTE

      The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.
    2. MUXMODE 1 through 5 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. Bootstrap are Special Configuration Pins, latched on rising edge of PORn / RESETFULLn. These are not programable MUXMODE.
    4. An empty box means Not Applicable.
  5. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • IOD = Input or Open-drain Output
    • IOZ = Input or Three-state Output
    • OZ = Three-state Output
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor.
  6. BALL RESET STATE: The state of the terminal at power-on reset:
    • DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable.
  7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal:
    • DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • DRIVE CLK (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable.

    8. For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see chapter Device Configuration of the Device TRM.

  8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal.
    An empty box means Not Applicable.
  9. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply). An empty box means Not Applicable.
  10. POWER: The voltage supply that powers the terminal IO buffers.
    An empty box means Not Applicable.
  11. HYS: Indicates if the input buffer has hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis

      • An empty box means No.

    12. For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.

  12. BUFFER TYPE: This column describes the associated output buffer type.

    13. An empty box means Not Applicable.

    For drive strength of the associated output buffer, refer to Section 5.7, Electrical Characteristics.

  13. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • An empty box means No pull.
  14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx registers:
    • 0: Logic 0 driven on the input signal port of the peripheral.
    • 1: Logic 1 driven on the input signal port of the peripheral.
    • An empty box means Not Applicable.

    15. NOTE

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration.

    NOTE

    When a pad is set into a multiplexing mode that is not defined by pin multiplexing, behavior of that pad is undefined, this configuration shall be avoided.
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