8.4.5.2.1 Writing to the CDCM6208

To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208. This bit signals if a read (first bit high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208 with each rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the target register in the register file. The 16 bits that follow are the data payload. If the host sends an incomplete message, (i.e. the host de-asserts the SCS pin high prior to a complete message transmission), then the CDCM6208 aborts the transfer, and device makes no changes to the register file or the hardware. Figure 42 shows the format of a write transaction on the CDCM6208 SPI port. The host signals the CDCM6208 of the completed transfer and disables the SPI port by de-asserting the SCS pin high.