In FPWM switching operation, the device enters bypass mode when the OVP status is triggered for at least 30 μs (V_OVTH-DLY) and V_CSP-CSN is greater than 6 mV (V_CS-FWD), indicating positive inductor current. To exit bypass mode the either the OVP status is cleared or V_SW-SENSE is less than -150 mV (V_I-NEG-BYP). Current flow from V_LOAD to V_SUPPLY can occur in bypass mode while operating in FPWM. Once the high-side FET is disabled, the device enters active mode. The proper conditions must be achieved to enter bypass mode again. See Table 7-2 for details on how the device enters and exits bypass mode.