With a logic high on the FPWM input, the device is locked in PWM mode. This operation is maintained, even at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current limit of I_NEG is imposed to prevent damage to the low-side FET of the regulator. When in FPWM the converter synchronizes to any valid clock signal on the SYNC input (see Section 8.4.3 and Section 8.4.4.

When constant frequency operation is more important than light load efficiency, pull the LM53625/35-Q1 FPWM input high or provide a valid synchronization input. Once activated, this feature ensures that the switching frequency stays above the AM frequency band, while operating between the minimum and maximum duty cycle limits. Essentially, the diode emulation feature is turned off in this mode. This means that the device remains in CCM under light loads. Under conditions where the device must reduce the on time or off time below the ensured minimum, the frequency reduces to maintain the effective duty cycle required for regulation. This can occur for high input/output voltage ratios.

With the FPWM pin pulled low (normal mode), the diode emulation feature is activated. Device operation is the same as above; however, the regulator goes into DCM operation when the valley of the inductor current reaches zero.

This feature may be activated and deactivated while the part is regulating without removing the load. This feature activates and deactivates gradually, over approximately 40 µs, preventing perturbation of output voltage. When in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the regulators output to its input. In this case, care must be taken to ensure that a large enough input capacitor is used to absorb this reverse current.