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SNVSBY3A November 2020 – April 2021 TLV840-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DBV|5
- MPDS018T

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.6 Timing Requirements

At 0.7 V ≤ V_DD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, output reset load (C_LOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typical values are at T_A = 25℃

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_{P_HL}	Propagation detect delay for VDD falling below V_IT–	V_DD: (V_IT++ 10%) to (V_IT– – 10%)⁽¹⁾	30	50	µs
t_D	Reset time delay	CT pin = Open or NC (V_IT-- 10%) to (V_IT+ + 10%)	40	80	µs
		CT pin = 10 nF	6.2		ms
		CT pin = 1 µF	619		ms
t_{GI_VIT–}	Glitch immunity V_IT–	5% V_IT– overdrive⁽²⁾	10		µs
t_STRT	Startup Delay ⁽³⁾	CT pin = Open or NC		300	µs
t_{MR_PW}	MR pin pulse duration to assert reset ⁽⁴⁾		500		ns
t_{MR_RES}	Propagation delay from MR low to reset assertion	V_DD = 3.3 V, MR = V_{MR_H}to V_{MR_L}	1		µs
t_{MR_tD}	Delay from MR release to reset deassert	V_DD = 3.3 V, MR = V_{MR_L}to V_{MR_H}	t_D		ms

(1) t_{P_HL} measured from threshold trip point (V_IT–) to RESET assert. V_IT+ = V_IT– + V_HYS

(2) Overdrive % = [(V_DD/ V_IT–) – 1] × 100%

(3) When VDD starts from less than the specified minimum V_DD and then exceeds V_IT-, reset is release after the startup delay (t_STRT), a capacitor at CT pin will add t_D delay to t_STRT time

(4) Refer section on Manual Reset Input for min pulse width needed on MR pin