ZHCSAF5A OCTOBER   2012  – September 2016 TPS51716

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDDQ Switch Mode Power Supply Control
      2. 7.3.2  VREF and REFIN, VDDQ Output Voltage
      3. 7.3.3  Soft-Start and Powergood
      4. 7.3.4  Power State Control
      5. 7.3.5  VDDQ Overvoltage and Undervoltage Protection
      6. 7.3.6  VDDQ Out-of-Bound Operation
      7. 7.3.7  VDDQ Overcurrent Protection
      8. 7.3.8  VTT and VTTREF
      9. 7.3.9  VTT Overcurrent Protection
      10. 7.3.10 V5IN Undervoltage Lockout (UVLO) Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin Configuration
      2. 7.4.2 Discharge Control
      3. 7.4.3 D-CAP2 Mode Operation
      4. 7.4.4 Light-Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Components Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 文档支持
      1. 11.2.1 接收文档更新通知
      2. 11.2.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RUK Package
20-Pin WQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DRVH 14 O High-side MOSFET gate driver output.
DRVL 11 O Low-side MOSFET gate driver output.
GND 7 — Signal ground.
MODE 19 I Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2)
PGND 10 — Gate driver power ground. RDS(on) current sensing input(+).
PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation.
SW 13 I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–).
S3 17 I S3 signal input. (See Table 1)
S5 16 I S5 signal input. (See Table 1)
TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC = 4700 ppm/°C.
VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF 6 O 1.8-V reference output
VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
VTTGND 4 — Power ground for VTT LDO
VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS 1 I VTT output voltage feedback.
V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal pad — — Thermal pad. Connect directly to system GND plane with multiple vias.
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