Figure 7-2 shows the output stage of the UCC27532-Q1 device. The UCC27532-Q1 device features a unique architecture on the output stage which delivers the highest peak-source current when it is most needed during the Miller plateau region of the power switch turnon transition (when the power switch drain or collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak sourcing current enabling fast turnon.

Figure 7-2 UCC27532-Q1 Gate-Driver Output Stage

The R_OH parameter (see Section 6.5) is a DC measurement and is representative of the on-resistance of the P-Channel device only because the N-Channel device is turned-on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by R_OH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The R_OL parameter (see Section 6.5), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In UCC27532-Q1 device, the effective resistance of the hybrid pullup structure is approximately 3 × R_OL.

The UCC27532-Q1 device is capable of delivering 2.5-A source, 5-A Sink (asymmetrical drive) at VDD = 18 V. Strong sink capability in asymmetrical drive results in a very low pulldown impedance in the driver output stage which boosts immunity against the parasitic Miller turnon (high slew-rate dV/dt turnon) effect that is seen in both IGBT and FET power switches.

An example of a situation where Miller turnon is a concern is synchronous rectification (SR). In SR application, the dV/dt occurs on MOSFET drain when the MOSFET is already held in the off state by the gate driver. The current charging the C_GD Miller capacitance during this high dV/dt is shunted by the pulldown stage of the driver. If the pulldown impedance is not low enough then a voltage spike can result in the V_GS of the MOSFET, which can result in spurious turnon. This phenomenon is illustrated in Figure 7-3.

Figure 7-3 Low Pulldown Impedance in the UCC27532-Q1 Device (Output Stage Mitigates Miller Turnon Effect)

The driver output voltage swings between VDD and GND providing rail-to-rail operation because of the MOS output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low impedance to switching overshoots and undershoots which means that in many cases, external Schottky diode clamps can be eliminated.