The device integrates extensive error detection and monitoring features. These features allow the design of a robust system that protects against a variety of system related failure modes. When one of the monitored warnings or faults occurs, if unmasked, the nFLT1 output (for faults) or the nFLT2 output (for warnings) pulls low. All of the fault and warning bits have corresponding configuration bits that allow the user to mask the error or fault from showing up on the nFLT* output. The naming convention is straightforward. The mask bit is in a CFG* register and is named the same as the fault with the addition of an "_P". For example, a power FET short circuit current fault is indicated in the register bit STATUS3[SC_FAULT] (STATUS3)and the mask bit is CFG9[SC_FAULT_P] (CFG9). Throughout this document, the different warning/error bit locations are indicated in the functional description of the block where the warning/fault is monitored. When masked, the nFLT* indication does not occur, but the STATUS* bits still indicate the warning/fault condition. The device classifies error events into two categories, Warnings and Faults, and takes different device actions depending on the error classification.

The Warning error class is used to report non-critical fault conditions. Warning errors are only reported with no action taken to affect the gate driver output or any other block. When a warning condition occurs, it is reported in on of the STATUS* registers and, if unmasked, the nFLT2 output is driven low. The nFLT2 indication for warning is cleared by a successful SPI read of the corresponding status register. Once cleared, warning indication is not repeated until the warning condition is removed and reapplied. For example, in an over temperature warning condition, after reading/clearing the bit the temperature must cool down to the normal operating range and then heat up again to the over temperature warning threshold for the error flag to be reasserted. The status bit always indicates the current state of the warning, and is not cleared until the error condition is removed.

The Fault error class is used to report critical fault conditions. Fault errors have the ability to shut down the gate driver when they occur. When a fault condition occurs, it is reported in one of the STATUS* registers and, if unmasked, the nFLT1 output is driven low. Many faults have a corresponding configuration bit that enables the user to select the functional safe state of the driver when that fault occurs when the fault is not masked. These bits are in the CFG* registers, with bit names that start with "FS_STATE_". Throughout this document, the FS_STATE locations are indicated in the functional description of the block where the fault is monitored. The available options for the output state, depending on the fault, are PL (OUTL pulled low), PH (OUTH pulled high), or no action (gate driver output ignores the fault and continues normal operation). Faults are cleared when the condition is removed, and the CONTROL2[CLR_STAT_REG] bit (CONTROL2) is written. Fault indication reasserts as long as the fault condition exists and is unmasked. Table 7-1 provides an extensive list and details for the available faults and warnings.