16.4 Initialization and Configuration
To enable and initialize the EPI controller, the following steps are necessary:
- Enable the EPI module using the RCGCEPI register, see Section 4.2.89.
- Enable the clock to the appropriate GPIO module using the RCGCGPIO registers (see Section 4.2.87). To find out which GPIO port to enable, see the device-specific data sheet.
- Set the GPIO AFSEL bits for the appropriate pins, see Section 17.5.10. To determine which GPIOs to configure, see the device-specific data sheet.
- Configure the GPIO current level and/or slew rate as specified for the mode selected, see Section 17.5.11 and Section 17.5.17.
- Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate pins (see Section 17.5.22 and the device-specific data sheet).
- Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the MODE field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed) using the appropriate mode configuration EPI Host Bus Configuration (EPIHBnCFGn) registers for the desired chip-select configuration. Set the EPI Main Baud Rate (EPIBAUD) and EPI Main Baud Rate 2 (EPIBAUD2) register if the baud rate must be slower than the system clock rate.
- Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The selected start address and range is dependent on the type of external device and maximum address (as appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to 0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to 0x3 for 256MB. If using General-Purpose mode and no address at all, program the EPADR field to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field to 0x0 for 256 bytes.
- To read or write directly, use the mapped address area (configured with the EPIADDRMAP register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked until the value is retrieved.
- To perform a nonblocking read, see Section 16.3.2.
NOTE
The application should not attempt external access until eight system clock cycles after the EPI has been fully configured.
NOTE
When a MODE field has been programmed in the EPICFG register, the application should reset all configuration registers before programming to a new MODE value.
The following subsections describe the initialization and configuration for each of the modes of operation. Initialize everything properly to ensure correct operation. Control of the GPIO states is also important, as changes may cause the external device to interpret pin states as actions or commands (see ). Normally, a pullup or pulldown is needed on the board to at least control the chip-select or chip-enable as the GPIOs come out of reset in high-impedance.