Revision History
Changes from October 27, 2017 to October 25, 2018
- Corrected the enumerated values 0x0, 0x1, and 0x2 for the ALTCLK bit in Table 4-24, ALTCLKCFG Register Field DescriptionsGo
- Updated the first paragraph in Section 7.2.3.5, Execute-Only ProtectionGo
- Updated Figure 9-2, AES – ECB Feedback ModeGo
- Updated Figure 9-5, AES – CFB Feedback ModeGo
- Updated Figure 9-7, AES – XTS OperationGo
- Changed EN0REF_CLK to EN0RREF_CLK throughout "Ethernet Controller" chapter to match data sheetsGo
- Removed GPIO column from Table 15-1, MII and RMII Signals; see device-specific data sheet for pin assignmentsGo
- Added missing arrows and text in Figure 15-11, System Time Update Using Fine Correction MethodGo
- Added comments that RTS and CTS are active low in Section 26.3.6.2.1, Hardware Flow Control (RTS and CTS)Go