米6体育平台手机版

SLDA021B March 2014 – February 2020 AM3892 , AM3894

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Revision History

Changes from A Revision (August 2015) to B Revision

Removed "Typically between 17 mm and 25 mm in body size, but not limited to" and "Thermally enhanced with a metal, heat-dissipative lid" from Generic Product Description ListGo
Changed from Mass: 2.2 to 7.5g to 0.2 to 0.3 g throughout documentGo
Deleted "Solder mask defined (SMD) — The solder mask opening is smaller than the metal pad." under non-soldier mask defined (NSMD). Go
Changed can be exposed "when trace routing is dense" to can be exposed "if not properly dimensioned,"Go
Removed 2.1.2 Solder-Mask-Defined (SMD) LandGo
Removed SMD from Solder Mask Type, SMO=0.35, Pad Size=0.45 from Table 1.Go
Removed BGA arrays and information from PCB routing sectionGo
Removed "Routing of 0.6hmm pitch Via Channel™ BGA Arrays SectionGo
Removed from table 2: BGA Array Type=Via-Channel, Via Diameter=20 mil, 18 mil, Via Hole Size=12-10 mil, 10-8 mil, Trace Size=4 mil, 4 mil, Clearance=4 mil, 4 mil, Micro Vias?=No, NoGo
Removed from table 2 on Standard BGA Array Type: Via Diameter=12 mil, Via Hole Size=6 mil, Trace Size=4 mil, Clearance= 4=mil, Micro Vias?=YesGo
Removed PCB Feature Sizes SectionGo
Removed 2.2.4.2 PCB Layer Count for Via Channel™ BGA arrays section and title Go
Removed Figure 9 Acceptable Solder Paste Alignment and Figure 10 Unacceptable Solder Paste alignment and all references to themGo
Removed "To simulate a worst-case paste alignment condition, prints were intentionally offset by 100μm (0.004”) in both X and Y directions. During the laboratory testing, the offset prints produced satisfactory results, with no solder defects formed. It should be noted that the tested offsets were extreme conditions and, while they can occur in production environments, are generally considered outside of the typical process window for most SMT assemblies of this complexity level." after "and the print should be rejected." in Section 3.3Go
Changed "If components are removed from their protective storage environment and exposed to ambient environment (≤30°C/60%RH) for more than 72 hours" to 168 hoursGo
Removed Figure 11 Example of X-Ray Image of Intentional Component Placement Offset and Figure 12 Example of X-Ray of Component Centered after Reflow Process and referencesGo
Removed section 4.9 Orientation Indicatior and Figure 13 Example of Orientation IndicatorsGo
Added Technical Specifications an d Packaging Information sectionsGo
Added package drawing Go
Removed "When designing with Via Channel Array™ technology, escape routing can be accomplished with a 4-layer PCB design and standard 20/10 PTH vias. High Density Interconnect PCB technology is not necessary. By depopulating balls from a full array in strategic locations, the Via Channel™ approach allocates space within the component footprint to allow complete signal routing with standard size traces and vias. This option greatly reduces PCB fabrication costs when compared with typical 0.65mm BGA packages." after ...each design element on PCB performance Go