SLLSEY7F June 2017 – April 2020
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VCC1 VOLTAGE SUPPLY | |||||||
VIT+ (UVLO1) | Positive-going UVLO threshold voltage (VCC1) | 2.25 | V | ||||
VIT– (UVLO1) | Negative-going UVLO threshold (VCC1) | 1.7 | V | ||||
VHYS (UVLO1) | UVLO threshold hysteresis (VCC1) | 0.2 | V | ||||
ICC1 | VCC1 supply quiescent current | ISO1211 | EN = VCC1 | 0.6 | 1 | mA | |
ISO1212 | 1.2 | 1.9 | |||||
LOGIC I/O | |||||||
VIT+ (EN) | Positive-going input logic threshold voltage for EN pin | 0.7 × VCC1 | V | ||||
VIT– (EN) | Negative-going input logic threshold voltage for EN pin | 0.3 × VCC1 | V | ||||
VHYS(EN) | Input hysteresis voltage for EN pin | 0.1 × VCC1 | V | ||||
IIH | Low-level input leakage at EN pin | EN = GND1 | –10 | μA | |||
VOH | High-level output voltage on OUTx | VCC1 = 4.5 V; IOH = –4 mA
VCC1 = 3 V; IOH = –3 mA VCC1= 2.25 V; IOH = –2 mA, see Figure 10 |
VCC1 – 0.4 | V | |||
VOL | Low-level output voltage on OUTx | VCC1 = 4.5 V; IOH = 4 mA
VCC1 = 3 V; IOH = 3 mA VCC1= 2.25 V ; IOH = 2 mA, see Figure 10 |
0.4 | V | |||
CURRENT LIMIT | |||||||
I(INx+SENSEx),TYP | Typical sum of current drawn from IN and SENSE pins across temperature | RTHR = 0 Ω, RSENSE = 562 Ω, VSENSE = 24 V,
–40°C < TA < 125°C, see Figure 11 |
2.2 | 2.47 | mA | ||
I(INx+SENSEx) | Sum of current drawn from IN and SENSE pins | RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
–60 V < VSENSE < 0 V, see Figure 11 |
–0.1 | µA | |||
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
5 V < VSENSE < VIL, see Figure 11 |
1.9 | 2.5 | mA | ||||
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
VIL < VSENSE < 30 V, see Figure 11 |
2.05 | 2.75 | |||||
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
30 V < VSENSE < 36 V, see Figure 11 |
2.1 | 2.83 | |||||
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
36 V < VSENSE < 60 V(1), see Figure 11 |
2.1 | 3.1 | |||||
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
–60 V < VSENSE < 0 V, see Figure 11 |
–0.1 | µA | |||||
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
5 V < VSENSE < VIL, see Figure 11 |
5.3 | 6.8 | mA | ||||
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
VIL < VSENSE < 36 V(1), see Figure 11 |
5.5 | 7 | |||||
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
36 V < VSENSE < 60 V(1), see Figure 11 |
5.5 | 7.3 | |||||
VOLTAGE TRANSITION THRESHOLD ON FIELD SIDE | |||||||
VIL | Low level threshold voltage at module input (including RTHR) for output low | RSENSE = 562 Ω, RTHR = 0 Ω, see Figure 11 | 6.5 | 7 | V | ||
RSENSE = 562 Ω, RTHR = 1 kΩ, see Figure 11 | 8.7 | 9.2 | |||||
RSENSE = 562 Ω, RTHR = 4 kΩ, see Figure 11 | 15.2 | 15.8 | |||||
VIH | High level threshold voltage at module input (including RTHR) for output high | RSENSE = 562 Ω, RTHR = 0 Ω, see Figure 11 | 8.2 | 8.55 | V | ||
RSENSE = 562 Ω, RTHR = 1 kΩ, see Figure 11 | 10.4 | 10.95 | |||||
RSENSE = 562 Ω, RTHR = 4 kΩ, see Figure 11 | 17 | 18.25 | |||||
VHYS | Threshold voltage hysteresis at module input | RSENSE = 562 Ω, RTHR = 0 Ω, see Figure 11 | 1 | 1.2 | V | ||
RSENSE = 562 Ω, RTHR = 1 kΩ, see Figure 11 | 1 | 1.2 | |||||
RSENSE = 562 Ω, RTHR = 4 kΩ, see Figure 11 | 1 | 1.2 |