SNAS605AS March   2013  – May 2020 LMK04821 , LMK04826 , LMK04828

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
    1. 5.1 Device Configuration Information
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Typical Characteristics – Clock Output AC Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation Vs. Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1  Jitter Cleaning
      2. 9.1.2  JEDEC JESD204B Support
      3. 9.1.3  Three PLL1 Redundant Reference Inputs
      4. 9.1.4  VCXO/Crystal Buffered Output
      5. 9.1.5  Frequency Holdover
      6. 9.1.6  PLL2 Integrated Loop Filter Poles
      7. 9.1.7  Internal VCOs
        1. 9.1.7.1 VCO1 Divider (LMK04821 only)
      8. 9.1.8  External VCO Mode
      9. 9.1.9  Clock Distribution
        1. 9.1.9.1 Device Clock Divider
        2. 9.1.9.2 SYSREF Clock Divider
        3. 9.1.9.3 Device Clock Delay
        4. 9.1.9.4 SYSREF Delay
        5. 9.1.9.5 Glitchless Half Step and Glitchless Analog Delay
        6. 9.1.9.6 Programmable Output Formats
        7. 9.1.9.7 Clock Output Synchronization
      10. 9.1.10 Zero-Delay
      11. 9.1.11 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How To Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
        2. 9.3.3.2 Dynamic Digital Delay
        3. 9.3.3.3 Single and Multiple Dynamic Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
      6. 9.3.6 Digital Lock Detect
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 Entering Holdover
        3. 9.3.7.3 During Holdover
        4. 9.3.7.4 Exiting Holdover
        5. 9.3.7.5 Holdover Frequency Accuracy and DAC Performance
        6. 9.3.7.6 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Device Functional Modes
      1. 9.4.1 Dual PLL
      2. 9.4.2 Zero-Delay Dual PLL
      3. 9.4.3 Single-Loop Mode
      4. 9.4.4 Single-Loop Mode With External VCO
      5. 9.4.5 Distribution Mode
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 SPI LOCK
        2. 9.5.1.2 SYSREF_CLR
        3. 9.5.1.3 RESET Pin
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
    7. 9.7 Device Register Descriptions
      1. 9.7.1 System Functions
        1. 9.7.1.1 RESET, SPI_3WIRE_DIS
        2. 9.7.1.2 POWERDOWN
        3. 9.7.1.3 ID_DEVICE_TYPE
        4. 9.7.1.4 ID_PROD[15:8], ID_PROD
        5. 9.7.1.5 ID_MASKREV
        6. 9.7.1.6 ID_VNDR[15:8], ID_VNDR
      2. 9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
        1. 9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
        2. 9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
        3. 9.7.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
        4. 9.7.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
        5. 9.7.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
        6. 9.7.2.6 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
        7. 9.7.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
      3. 9.7.3 SYSREF, SYNC, and Device Config
        1. 9.7.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
        2. 9.7.3.2  SYSREF_CLKin0_MUX, SYSREF_MUX
        3. 9.7.3.3  SYSREF_DIV[12:8], SYSREF_DIV[7:0]
        4. 9.7.3.4  SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
        5. 9.7.3.5  SYSREF_PULSE_CNT
        6. 9.7.3.6  PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
        7. 9.7.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
        8. 9.7.3.8  DDLYdSYSREF_EN, DDLYdX_EN
        9. 9.7.3.9  DDLYd_STEP_CNT
        10. 9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
        11. 9.7.3.11 SYNC_DISSYSREF, SYNC_DISX
        12. 9.7.3.12 Fixed Registers (0x145, 0x171 - 0x172)
      4. 9.7.4 (0x146 - 0x149) CLKin Control
        1. 9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
        2. 9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
        3. 9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
        4. 9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
      5. 9.7.5 RESET_MUX, RESET_TYPE
      6. 9.7.6 (0x14B - 0x152) Holdover
        1. 9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
        2. 9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
        3. 9.7.6.3 DAC_TRIP_LOW
        4. 9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
        5. 9.7.6.5 DAC_CLK_CNTR
        6. 9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
        7. 9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
      7. 9.7.7 (0x153 - 0x15F) PLL1 Configuration
        1. 9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]
        2. 9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]
        3. 9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]
        4. 9.7.7.4 PLL1_N
        5. 9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
        6. 9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
        7. 9.7.7.7 PLL1_R_DLY, PLL1_N_DLY
        8. 9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
      8. 9.7.8 (0x160 - 0x16E) PLL2 Configuration
        1. 9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]
        2. 9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
        3. 9.7.8.3 PLL2_N_CAL
        4. 9.7.8.4 PLL2_FCAL_DIS, PLL2_N
        5. 9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
        6. 9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
        7. 9.7.8.7 PLL2_LF_R4, PLL2_LF_R3
        8. 9.7.8.8 PLL2_LF_C4, PLL2_LF_C3
        9. 9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
      9. 9.7.9 (0x16F - 0x1FFF) Misc Registers
        1. 9.7.9.1  PLL2_PRE_PD, PLL2_PD
        2. 9.7.9.2  VCO1_DIV
        3. 9.7.9.3  OPT_REG_1
        4. 9.7.9.4  OPT_REG_2
        5. 9.7.9.5  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
        6. 9.7.9.6  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
        7. 9.7.9.7  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
        8. 9.7.9.8  RB_DAC_VALUE
        9. 9.7.9.9  RB_HOLDOVER
        10. 9.7.9.10 SPI_LOCK
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Lock Detect Frequency Accuracy
      1. 10.2.1 Minimum Lock Time Calculation Example
    3. 10.3 Driving CLKin and OSCin Inputs
      1. 10.3.1 Driving CLKin and OSCin Pins With a Differential Source
      2. 10.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
    4. 10.4 Output Termination and Biasing
      1. 10.4.1 LVPECL
      2. 10.4.2 LVDS/HSDS
    5. 10.5 Typical Applications
      1. 10.5.1 Design Example
        1. 10.5.1.1 Design Requirements
        2. 10.5.1.2 Detailed Design Procedure
          1. 10.5.1.2.1 Device Configuration and Simulation - PLLatinum Sim
          2. 10.5.1.2.2 Device Programming
        3. 10.5.1.3 Application Curves
    6. 10.6 System Examples
      1. 10.6.1 System Level Diagram
    7. 10.7 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Pin Connection Recommendations
      1. 11.1.1 VCC Pins and Decoupling
        1. 11.1.1.1 Clock Output Supplies
        2. 11.1.1.2 Low-Crosstalk Supplies
        3. 11.1.1.3 PLL2 Supplies
        4. 11.1.1.4 Clock Input Supplies
        5. 11.1.1.5 Unused Clock Inputs/Outputs
    2. 11.2 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 PLLatinum Sim
        2. 13.1.1.2 TICS Pro
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from AR Revision (December 2015) to AS Revision

Changes from AQ Revision (August 2014) to AR Revision

  • Added Support for 105°C thermal pad temperature.Go
  • Changed from I/O to I for pin 6 in Pin Functions table. Go
  • Deleted programmable status pin in Description column for pin 6 in Pin Functions table.Go
  • Changed from No connection to Do not connect for pins 7, 8, 9 in Pin Functions table. Go
  • Changed to Reference Clock Input Port 1 for PLL 1 for Pins 34, 35 in Pin Functions.Go
  • Added Reference Clock Input Port 2 for PLL1 for pins 40, 41 in Pin Functions. Go
  • Added ESD RatingsGo
  • Added PCB temperature in Recommended Operating Conditions.Go
  • Added Digital Input Timing in Electrical Characteristics. Go
  • Changed Detailed block diagrams for LMK04821 and LMK04826/8. Go
  • Added 6 to DCLKout0 sequence and 7 to SDCLKout1 sequence in Figure 12.Go
  • Added 6 to DCLKout0 sequence and 7 to SDCLKout1 sequence in Figure 13.Go
  • Added For each SDCLKoutY being used in SYNC/SYSREF.Go
  • Deleted "SDCLKoutY_PD as required per output. " in Table 1.Go
  • Added footnote starting SDCLKoutY_PD = 0 as... in Table 1. Go
  • Added SDCLKout1_PD = 0, SDCLKout3_PD = 0 in Setup of SYSREF Example.Go
  • Changed DLD_HOLD_CNT to HOLDOVER_DLD_CNT in Holdover Mode - Automatic Exit of Holdover .Go
  • Changed Recommended Programming Sequence. Go
  • Added 0x171/0x172 to Register Map. Go
  • Added LMK04821 register setting.Go
  • Revised Register 0x143 table.Go
  • Added fixed register setting for 0x171Go
  • Added fixed register setting for 0x172 Go
  • Added LMK04821 register setting. Go
  • Added LMK04821 register setting. Go
  • Changed RB_PLL1_LD description. Go
  • Changed RB_PLL2_LD description. Go

Changes from AP Revision (June 2013) to AQ Revision

  • Changed data sheet flow and layout to conform with new TI standards. Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
  • Added values for LMK04821 under "Features" section. Go
  • Changed LMK04820 family to LMK0482x family. Go
  • Added values for LMK04821 in Device Configuration Information.Go
  • Added holdover DAC to pin 36 description in Pin Functions.Go
  • Changed Thermal Information header from LMK0482xB to LMK0482x. Go
  • Changed CLKinX_BUF_TYPE to CLKinX_TYPE in Electrical Characteristics.Go
  • Added values for LMK04821 under Internal VCO Specifications in Electrical Characteristics.Go
  • Added values for LMK04821 under Noise Floor in Electrical Characteristics.Go
  • Added values for LMK04821 under CLKout Closed Loop Phase Noise Specifications a Commercial Quality VCXO in Electrical Characteristics.Go
  • Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)CLKout for VCO0. Go
  • Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)CLKout for VCO1. Go
  • Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)CLKout for VCO0. Go
  • Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)CLKout for VCO1. Go
  • Added values for LMK04821 under CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO.Go
  • Added SDCLKoutY_HS = 0 for tsJESD204B in Electrical Characteristics.Go
  • Added Propagation Delay from CLKin0 to SDCLKoutY in Electrical Characteristics.Go
  • Changed VOH TEST CONDITIONS to = 3 or 4 and VOL TEST CONDITIONS to 3, 4, or 6 under DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) subheading in Electrical Characteristics.Go
  • Changed Digital Inputs (SCK, SDIO, CS*) IIH VIH = VCC min line from 5 µA to –5 µA.Go
  • Added footnote that LMK04821 has no DCLKoutX or SDCLKoutY outputs on at power up, only OSCout. Go
  • Added 4 wire mode read back has same timing as SDIO pin, R/W bit = 0 is for SPI write, R/W bit = 1 is for SPI read, W1 and W0 shall be written as 0.Go
  • Added LMK04821 phase noise graphs under Clock Output AC Characteristics.Go
  • Added link to AN-912 Application Report.Go
  • Changed from Glitchless Half Shift to Glitchless Half Step.Go
  • Added LMK04821 detailed block diagram.Go
  • Changed block from SDCLKoutY_POL to DCLKoutX_POL in Figure 12.Go
  • Added SYSREF_CLKin0_MUX block to Figure 13 image.Go
  • Changed Figure 13 to show that FB_MUX SYSREF input comes from SYSREF Divider, not SYSREF_MUX.Go
  • Changed term pulsor to pulser throughout.Go
  • Changed DCLKout0_1_DIV to DCLKout0_DIV; DCLKout2_3_DIV to DCLKout2_DIV; DCLKout4_5_DIV to DCLKout4_DIV.Go
  • Added DCLKout4_DIV = 20.Go
  • Added DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0.Go
  • Changed text to read, Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH, DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH, DCLKout4_DDLY_CNTL, SYSREF_DDLY. Go
  • Added = 1 in SYSREF Request. Go
  • Changed step numbers in dynamic delay and references to steps to be correct, step 8 was duplicated. Go
  • Added note LMK04821 includes VCO1 divider on VCO1 output..Go
  • Added note LMK04821 includes VCO1 divider on VCO1 output..Go
  • Added R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read. Go
  • Added If using LMK04821, program register 0x174 in Recommended Programming Sequence.Go
  • Added SYSREF_CLKin0_MUX and VCO1_DIV to register map.Go
  • Added CLKin_OVERRIDE bit to register map. Go
  • Changed from half shift to half step.Go
  • Changed definition of SDCLKoutY_DDLY value of 0 from Reserved to Bypass.Go
  • Changed from Sets the polarity of SYSREF clocks to Sets the polarity of clock on SDCLKoutY when device clock output is selected with SDCLKoutY_MUX.Go
  • Changed Sets the polarity of the device clocks to Sets the polarity of the device clocks from the DCLKoutX outputs.Go
  • Added LMK04821 DCLKoutX_FMT power on reset values as powerdown.Go
  • Changed from SYSREF to SYSREF Divider in Source column of Register 0x13F.Go
  • Changed reserved to Off for CLKin1_OUT_MUX. Go
  • Changed reserved to Off for CLKin0_OUT_MUX. Go
  • Added CLKin_OVERRIDE bit.Go
  • Added LMK04821 register 0x174 for VCO1_DIV.Go
  • Deleted LMK04828 from Core line. Go
  • Added VCO1 Icc including VCO1 Divider for LMK04821.Go
  • Changed VCO1 Icc and power dissipated for LMK04828B/26B from 6 mA to 13.5 mA and 19.8 mW to 44.55 mW.Go

Changes from AO Revision (March 2013) to AP Revision

  • Changed datasheet title from LMK04828 to LMK0482xBGo
  • Changed LMK04828 family to LMK04820 family.Go
  • Changed image from LMK04828B to LMK0482xB.Go
  • Added LMK04826 to Device Configuration Information table.Go
  • Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz.Go
  • Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz.Go
  • Changed Thermal Information header from LMK04828B to LMK0482xB.Go
  • Added LMK04826 VCO Range SpecificationGo
  • Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz.Go
  • Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz.Go
  • Added LMK04826 KVCO specification.Go
  • Added clarification of LMK04828 specification vs LMK04826 specification for KVCO.Go
  • Added LMK04826 noise floor data.Go
  • Changed - clarified phase noise data section header.Go
  • Added LMK04826 phase noise data.Go
  • Added LMK04826 jitter data.Go
  • Added LMK04826 fCLKout-startup spec.Go
  • Added clarification of LMK04828 specification vs. LMK04826 specification for fCLKout-startup.Go
  • Added LMK04826B Phase Noise Performance Graph for VCO0.Go
  • Added LMK04826B Phase Noise Performance Graph for VCO1.Go
  • Added Added PLL2 loop filter bandwidth and phase margin info to plot.Go
  • Changed LMK04828 to LMK0482xB in VCXO/Crystal Buffered Output. Go
  • Changed LMK04828 to LMK0482xB in Status Pins.Go
  • Changed image from LMK04828 to LMK0482xB.Go
  • Changed - corrected value of PLL2_P selection to be 0 to correspond with register programming definition.Go
  • Changed image from LMK04828 to LMK0482xB.Go
  • Changed image from LMK04828 to LMK0482xB.Go
  • Added LMK04826 register setting.Go
  • Added LMK04826 register setting.Go
  • Added LMK04826 register setting.Go
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