| ADC |
ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt
Mode) is not Set |
Yes |
| ADC |
ADC: Degraded ADC Performance With ADCCLK Fractional
Divider |
Yes |
| ADC |
ADC: DMA Read of Stale Result |
Yes |
| Analog Subsystem |
Analog Subsystem: Writes to Bit 1 of the ADCDACLOOPBACK
Register are not Functional |
Yes |
| BOR |
BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn
Pulses |
Yes |
| CMPSS |
CMPSS: COMPxLATCH May Not Clear Properly Under Certain
Conditions |
Yes |
| CMPSS |
CMPSS: A CMPSS Glitch can Occur if Comparator Input Pin has AGPIO
Functionality and ADC is Sampling the Input Pin |
Yes |
| DCAN |
DCAN: During DCAN FIFO Mode, Received Messages May be Placed
Out of Order in the FIFO Buffer |
Yes |
| MCAN |
MCAN: Message Order Inversion When Transmitting From Dedicated
Tx Buffers Configured With Same Message ID |
Yes |
| ePWM |
ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the
End of the Blanking Window |
Yes |
| ePWM |
ePWM: Trip Events Will Not be Filtered by the Blanking Window
for the First 3 Cycles After the Start of a Blanking
Window |
Yes |
| eQEP |
eQEP: Position Counter Incorrectly Reset on Direction Change
During Index |
Yes |
| FPU |
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p
Operation |
Yes |
| I2C |
I2C: Target Transmitter Mode, Standard Mode SDA Timings
Limitation |
Yes |
| LIN |
LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not
Set When Sync Field is Erroneous |
Yes |
| Memory |
Memory: Prefetching Beyond Valid Memory |
Yes |
| Boot ROM |
Boot ROM: Data Overrun With MCAN Bootloader on TMX
Devices |
Yes |
| Boot ROM |
Secure Live Firmware Update (LFU) Boot Modes are
Deprecated |
Yes |
| Flash |
Flash: Execution of Fapi_setActiveFlashBank() Without Disabling
Flash Prefetch may Cause ITRAP |
Yes |
| SYSTEM |
SYSTEM: HIC Illegal Read Error Flag Does not Get Asserted in
Pagesel=0 Mode |
Yes |
| SYSTEM |
SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a
System Hang |
Yes |
| Diagnostics |
Avoiding Spurious Interrupts While Using HWBIST |
Yes |
| PLL |
PLL Reference Clock Lost Detection: Missing Clock Flag may be
Incorrectly Activated |
Yes |
| SDFM |
SDFM: Dynamically Changing Threshold Settings (LLT, HLT),
Filter Type, or COSR Settings Will Trigger Spurious Comparator
Events |
Yes |
| SDFM |
SDFM: Dynamically Changing Data Filter Settings (Such as Filter
Type or DOSR) Will Trigger Spurious Data Acknowledge
Events |
Yes |
| SDFM |
SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields
CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock
Cycles can Corrupt SDFM State Machine, Resulting in Spurious
Comparator Events |
Yes |
| Watchdog |
Watchdog: WDKEY Register is not EALLOW-Protected |
Yes |