| ADC |
ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt
Mode) is not Set |
Yes |
Yes |
Yes |
| ADC |
ADC: Degraded ADC Performance With ADCCLK Fractional
Divider |
Yes |
Yes |
Yes |
| BOR |
BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn
Pulses |
Yes |
Yes |
Yes |
| CMPSS |
CMPSS: COMPxLATCH May Not Clear Properly Under Certain
Conditions |
Yes |
Yes |
Yes |
| CMPSS |
CMPSS: A CMPSS Glitch can Occur if Comparator Input Pin has
AGPIO Functionality and ADC is Sampling the Input
Pin |
Yes |
Yes |
Yes |
| DCAN |
During DCAN FIFO Mode, Received Messages May be Placed Out of
Order in the FIFO Buffer |
Yes |
Yes |
Yes |
| MCAN |
Message Order Inversion When Transmitting From Dedicated Tx
Buffers Configured With Same Message ID |
Yes |
Yes |
Yes |
| ePWM |
ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the
End of the Blanking Window |
Yes |
Yes |
Yes |
| ePWM |
ePWM: Trip Events Will Not be Filtered by the Blanking Window
for the First 3 Cycles After the Start of a Blanking
Window |
Yes |
Yes |
Yes |
| eQEP |
eQEP: Position Counter Incorrectly Reset on Direction Change
During Index |
Yes |
Yes |
Yes |
| Flash |
Flash: Single-Bit ECC Error Interrupt is Not
Generated |
Yes |
Yes |
Yes |
| FPU |
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p
Operation |
Yes |
Yes |
Yes |
| I2C |
I2C: Target Transmitter Mode, Standard Mode SDA Timings
Limitation |
Yes |
Yes |
Yes |
| LCM |
LCM: Consecutive Reset Cycles can Cause False LCM Compare
Error |
Yes |
Yes |
Yes |
| LIN |
LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not
Set When Sync Field is Erroneous |
Yes |
Yes |
Yes |
| Memory |
Memory: Prefetching Beyond Valid Memory |
Yes |
Yes |
Yes |
| SYSTEM |
SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a
System Hang |
Yes |
Yes |
Yes |
| PLL |
PLL Reference Clock Lost Detection: Missing Clock Flag may be
Incorrectly Activated |
Yes |
Yes |
Yes |
| Watchdog |
Watchdog: WDKEY Register is not EALLOW-Protected |
Yes |
Yes |
Yes |