SWRZ074C May 2017 – May 2021 IWR1443
| Advisory Number | Advisory Title | IWR1443 | ||
|---|---|---|---|---|
| ES1.0 | ES2.0 | ES3.0 | ||
| Main Subsystem | ||||
| MSS#01 | Available MSS Memory (RAM) for Customer Application is Smaller by 128 KB | X | X | |
| MSS#03A | Incorrect Handling of “Saturation” in FFT Hardware Accelerator’s Input / Output Formatter and Statistics Block | X | X | X |
| MSS#04A | Number of Samples (SRCACNT) Should be >3 for Correct Operation of FFT Hardware Accelerator | X | X | X |
| MSS#05A | Incorrect FFT Intermediate Stage Clip Status Indication | X | X | X |
| MSS#06 | Internal Pulls on QSPI Data Lines not Enabled by the Device Bootloader | X | X | |
| MSS#07A | MSS interrupt Number 106 Seen as Pending by the User Application | X | X | X |
| MSS#08 | ESM Group2 Interrupt (VIM Compare Error), Which is Mapped to FIQ Line, is Active When Control is Passed to Application | X | X | |
| MSS#09 | ESM Group1 Interrupt (NERROR_IN_SYNC) Seen as Pending by User Application – Can Lead to Interrupt if Unmasked | X | X | |
| MSS#13 | Incorrect Read from FFT Hardware Accelerator After Complex Multiplication Operation | X | X | X |
| MSS#14 | Asynchronous Assertion of SoC Warm Reset may not Work Reliably When Device Operating on PLL Clock | X | X | |
| MSS#15 | The IWR14xx ES1.0 and ES2.0 Devices Only Work With Spansion and Macronix Devices | X | X | See(1) |
| MSS#19 | DMA Read from Unimplemented Address Space may Result in DMA Hang Scenario | X | X | X |
| MSS#20 | Radar Frame Stuck due to Missing Synchronizer Logic in Hardware | X | X | X |
| MSS#21A | Issue with HWA Input Formatter 16 bit Real Signed Format | X | X | X |
| MSS#22 | CAN-FD: Message Transmitted With Wrong Arbitration and Control Fields | X | X | X |
| MSS#23 | HWA Read Registers Cannot be Read Reliably When the HWA is Executing a ParamSet Instruction | X | X | X |
| MSS#24 | Limitation With Peak Grouping Feature in Hardware Accelerator | X | X | X |
| MSS#25 | Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset Occurs | X | X | X |
| MSS#26 | DMA Requests Lost During Suspend Mode | X | X | X |
| MSS#27 | MibSPI in Slave Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1 | X | X | X |
| MSS#28 | A Data Length Error is Generated Repeatedly in Slave Mode When IO Loopback is Enabled | X | X | X |
| MSS#29 | Spurious RX DMA REQ From a Slave Mode MibSPI | X | X | X |
| MSS#30 | MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After Reading | X | X | X |
| MSS#31 | CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space | X | X | X |
| MSS#32 | DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A Packet | X | X | X |
| MSS#33 | MibSPI RAM ECC is Not Read Correctly in DIAG Mode | X | X | X |
| MSS#35 | EDMA TPTC Generates an Incorrect Address on the Read Interface, Causing one or More Data Integrity Failures, Hangs, or Extra Reads | X | X | X |
| MSS#37B | DCC Module Frequency Comparison can Report Erroneous Results | X | X | X |
| MSS#38A | GPIO Glitch During Power-Up | X | X | X |
| MSS#39 | The state of the MSS DMA is left pending and uncleared on any DMA MPU fault | X | X | X |
| MSS#40 | Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC | X | X | X |
| MSS#43A | Read-data from internal registers of PCR is not reliable. Shared PCS region protection is also not supported | X | X | X |
| MSS#44 | SYNC IN input pulse wider than 4usec can cause a FRC lockstep error | X | X | X |
| MSS#45 | Bootup failure during the serial flash busy state | X | X | X |
| Analog / Millimeter Wave | ||||
| ANA#01 | Noise Figure Degradation | X | ||
| ANA#02 | VCO#1 [76-77GHz] Minimum Frequency Falls Short of Target | X | ||
| ANA#03 | Spurs from LVDS Output Coupling into Synthesizer | X | ||
| ANA#04 | Receiver Gain Range Availability | X | ||
| ANA#06 | Return Loss Measurement on TX: S11 <
–9dB, RX S11 < –6.5dB (Accepted Value of < –10dB) |
X | ||
| ANA#07 | CSI2 Activity Coupling to Clock | X | X | |
| ANA#08A | Doppler Spur Observed at Certain RF Frequencies | X | X | X |
| ANA#10A(1) | Unreliable Readings from Synthesizer Supply Voltage Monitor | X | X | X |
| ANA#11A | TX, RX Gain Calibrations Sensitive to Large External Interference | X | X | X |
| ANA#12A | Second Harmonic (HD2) Present in the Receiver | X | X | X |
| ANA#13B | TX1 to TX3 Phase Mismatch Variation over Temperature is Double that of TX2/TX1 and TX3/TX2 Combinations | X | X | X |
| ANA#15 | Excessive TX-RX Coupling or Reflection can Lead to Saturated RX Output | X | X | X |
| ANA#16 | LVDS Coupling to Clock System | X | X | X |
| ANA#17A | On-Board Supply Ringing Induced Spur | X | X | X |
| ANA#18B | Spurs Caused due to Digital Activity Coupling to XTAL | X | X | X |
| ANA#20 | Occasional Failures Observed During Calibration of the Radar Subsystem | X | X | X |
| ANA#21A | Out of Band Radiated Spectral Emission | X | X | X |
| ANA#22A | Overshoot and Undershoot During Inter-Chirp Idle Time | X | X | X |
| ANA#24A | 40-MHz OSC CLKOUT Causing Spurs in 2D-FFT Spectrum | X | X | X |
| ANA#27 | Digital Temperature Sensor Having Higher Error | X | X | X |