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UCC21750
5.7kVrms ±10A, single-channel isolated gate driver w/ DESAT & internal miller clamp for IGBT/SiCFETs
Data sheet
UCC21750
- 5.7-kVRMS single channel isolated gate driver
- SiC MOSFETs and IGBTs up to 2121Vpk
- 33-V maximum output drive voltage (VDD – VEE)
- ±10-A drive strength and split output
- 150-V/ns minimum CMTI
- 200-ns response time fast DESAT protection
- 4-A Internal active miller clamp
- 400-mA soft turn-off when fault happens
- Isolated analog sensor with PWM output for
- Temperature sensing with NTC, PTC or thermal diode
- High voltage DC-link or phase voltage
- Alarm FLT on overcurrent and reset from RST/EN
- Fast enable and disable response on RST/EN
- Reject < 40-ns noise transient and pulse on input pins
- 12-V VDD UVLO with power good on RDY
- Inputs/outputs with over/under-shoot transient voltage immunity up to 5 V
- 130-ns (maximum) propagation delay and 30-ns (maximum) pulse/part skew
- SOIC-16 DW package with creepage and clearance distance > 8 mm
- Operating junction temperature –40°C to 150°C
- Safety-related certifications:
- Reinforced insulation per DIN EN IEC 60747-17 (VDE 0884-17)
- UL 1577 component recognition program
The UCC21750 is a galvanic isolated single channel gate driver designed for SiC MOSFETs and IGBTs up to 2121-V DC operating voltage with advanced protection features, best-in-class dynamic performance and robustness. The UCC21750 has up to ±10-A peak source and sink current.
The input side is isolated from the output side with SiO2 capacitive isolation technology, supporting up to 1.5-kVRMS working voltage, 12.8-kVPK surge immunity with longer than 40 years Isolation barrier life, as well as providing low part-to-part skew , and > 150-V/ns common mode noise immunity (CMTI).
The UCC21750 includes the state-of-art protection features, such as fast overcurrent and short circuit detection, shunt current sensing support, fault reporting, active miller clamp, and input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness. The isolated analog to PWM sensor can be used for easier temperature or voltage sensing, further increasing the drivers’ versatility and simplifying the system design effort, size, and cost.
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Technical documentation
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View all 15 Design & development
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Evaluation board
UCC21750QDWEVM-025 — Driving and protection evaluation board for SiC and IGBT transistors and power modules
The UCC21750QDWEVM-025 is a compact, single channel isolated gate driver board providing drive, bias voltages, desat feature based protection and diagnostic needed for SiC MOSFET and Si IGBT Power Modules housed in 150 x 62 x 17 mm and 106 x 62 x 30 mm packages. This TI EVM is based on 5.7-kVrms (...)
User guide: PDF
Evaluation board
UCC21750QDWEVM-054 — UCC21750 evaluation module for Wolfspeed® 1200-V SiC platforms
The UCC21750QDWEVM-054 is a compact half-bridge gate driver evaluation module consisting of two single-channel isolated gate drivers. The evaluation module provides supply voltage, drive, protection and monitoring needed for driving several different models of Wolfspeed® (...)
User guide: PDF
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs
PMP23223 — Smart isolated gate driver with bias supply reference design
This reference design demonstrates the combination of UCC21732 gate driver with a UCC14xxx series bias supply. This design can be used to drive a variety of power switches, including connecting directly to a Wolfspeed Silicon Carbide (SiC) field-effect transistor (FET) module. This reference design (...)
Test report: PDF
Reference designs
TIDA-01599 — TÜV SÜD-assessed safe torque off (STO) reference design for industrial drives (IEC 61800-5-2)
This reference design outlines a safe torque off (STO) subsystem for a three-phase inverter with CMOS input isolated IGBT gate drivers. The STO subsystem employs a dual-channel architecture (1oo2) with a hardware fault tolerance of 1 (HFT=1). It is implemented following a de-energize trip concept. (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (DW) | 16 | Ultra Librarian |
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