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UCC27211

ACTIVE

4-A, 120-V half bridge gate driver with 8-V UVLO and TTL inputs

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UCC27211A ACTIVE 4-A, 120-V half bridge gate driver with 8-V UVLO and negative voltage handling Improved robustness

Product details

Bootstrap supply voltage (max) (V) 110 Power switch MOSFET Input supply voltage (min) (V) 8 Input supply voltage (max) (V) 17 Peak output current (A) 4 Operating temperature range (°C) -40 to 140 Undervoltage lockout (typ) (V) 8 Rating Catalog Propagation delay time (µs) 0.02 Rise time (ns) 8 Fall time (ns) 7 Iq (mA) 0.001 Input threshold TTL Channel input logic TTL Switch node voltage (V) -12 Driver configuration Dual, Noninverting, TTL compatible
Bootstrap supply voltage (max) (V) 110 Power switch MOSFET Input supply voltage (min) (V) 8 Input supply voltage (max) (V) 17 Peak output current (A) 4 Operating temperature range (°C) -40 to 140 Undervoltage lockout (typ) (V) 8 Rating Catalog Propagation delay time (µs) 0.02 Rise time (ns) 8 Fall time (ns) 7 Iq (mA) 0.001 Input threshold TTL Channel input logic TTL Switch node voltage (V) -12 Driver configuration Dual, Noninverting, TTL compatible
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6 VSON (DRM) 8 16 mm² 4 x 4 WSON (DPR) 10 16 mm² 4 x 4
  • Drives two N-channel MOSFETs in high-side and low-side configuration with independent inputs
  • Maximum boot voltage 120V DC
  • 3.7A source, 4.5A sink output currents
  • Input pins can tolerate –10V to 20V and are independent of supply voltage range
  • TTL compatible input versions
  • 8V to 17V VDD operating range, (20V absolute maximum)
  • 7.2ns rise and 5.5ns fall time with 1000pF load
  • Fast propagation delay times (20ns typical)
  • 4ns delay matching
  • Symmetrical undervoltage lockout for high-side and low-side driver
  • All industry standard packages available (SOIC-8, PowerPAD™ SOIC-8, 4mm × 4mm SON-8 and 4mm × 4mm SON-10)
  • Specified from –40°C to 150°C
  • Drives two N-channel MOSFETs in high-side and low-side configuration with independent inputs
  • Maximum boot voltage 120V DC
  • 3.7A source, 4.5A sink output currents
  • Input pins can tolerate –10V to 20V and are independent of supply voltage range
  • TTL compatible input versions
  • 8V to 17V VDD operating range, (20V absolute maximum)
  • 7.2ns rise and 5.5ns fall time with 1000pF load
  • Fast propagation delay times (20ns typical)
  • 4ns delay matching
  • Symmetrical undervoltage lockout for high-side and low-side driver
  • All industry standard packages available (SOIC-8, PowerPAD™ SOIC-8, 4mm × 4mm SON-8 and 4mm × 4mm SON-10)
  • Specified from –40°C to 150°C

The UCC27211 driver is based on the popular UCC27201 MOSFET drivers, but offer several significant performance improvements. Peak output pull-up and pull-down current has been increased to 3.7A source and 4.5A sink, thereby allowing for driving large power MOSFETs with minimized switching losses during the transition through the Miller Plateau of the MOSFET. The input structure is now able to directly handle –10VDC, which increases robustness and also allows direct interface to gate-drive transformers without using rectification diodes. The inputs are also independent of supply voltage and have a maximum rating of 20V.

The switching node (HS pin) can handle –(24 – VDD) V maximum which allows the high-side channel to be protected from inherent negative voltages caused parasitic inductance and stray capacitance. UCC27211 (TTL inputs) has increased input hysteresis allowing for interface to analog or digital PWM controllers with enhanced noise immunity.

The low-side and high-side gate drivers are independently controlled and matched to 4 ns between the turnon and turnoff of each other. An on-chip 120V rated bootstrap diode eliminates the external discrete diodes.

Undervoltage lockout is provided for both the high-side and the low-side drivers providing symmetric turnon and turnoff behavior and forcing the outputs low if the drive voltage is below the specified threshold.

The UCC27211 driver is based on the popular UCC27201 MOSFET drivers, but offer several significant performance improvements. Peak output pull-up and pull-down current has been increased to 3.7A source and 4.5A sink, thereby allowing for driving large power MOSFETs with minimized switching losses during the transition through the Miller Plateau of the MOSFET. The input structure is now able to directly handle –10VDC, which increases robustness and also allows direct interface to gate-drive transformers without using rectification diodes. The inputs are also independent of supply voltage and have a maximum rating of 20V.

The switching node (HS pin) can handle –(24 – VDD) V maximum which allows the high-side channel to be protected from inherent negative voltages caused parasitic inductance and stray capacitance. UCC27211 (TTL inputs) has increased input hysteresis allowing for interface to analog or digital PWM controllers with enhanced noise immunity.

The low-side and high-side gate drivers are independently controlled and matched to 4 ns between the turnon and turnoff of each other. An on-chip 120V rated bootstrap diode eliminates the external discrete diodes.

Undervoltage lockout is provided for both the high-side and the low-side drivers providing symmetric turnon and turnoff behavior and forcing the outputs low if the drive voltage is below the specified threshold.

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Technical documentation

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Type Title Date
* Data sheet UCC27211 120V, 3.7A/4.5A Half-Bridge Driver with 8V UVLO datasheet (Rev. G) PDF | HTML 18 Jul 2024
Application note Voltage Fed Full Bridge DC-DC & DC-AC Converter High-Freq Inverter Using C2000 (Rev. D) 07 Apr 2021
Application note Understanding and comparing peak current capability of gate drivers PDF | HTML 30 Mar 2021
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Application note Hybrid Battery Charger with Load Control for Telecom Equipments (Rev. A) 09 May 2018
More literature Improving System Efficiency With a New Intermediate-Bus Architecture 20 Sep 2011

Design & development

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Package Pins CAD symbols, footprints & 3D models
HSOIC (DDA) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
VSON (DRM) 8 Ultra Librarian
WSON (DPR) 10 Ultra Librarian

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