TMS320DM355

Name: TMS320DM355
Brand: TI
SKU: TMS320DM355
Price: 17.103 USD

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数字媒体片上系统 (DMSoC)

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数据表

document-pdfAcrobat TMS320DM355 Digital Media System-on-Chip (DMSoC) 数据表 (Rev. G) (英语)

勘误

document-pdfAcrobat
TMS320DM355 Digital Media System-on-Chip Silicon Errata (Revs 1.1, 1.3 and 1.4) (Rev. E) (英语)

TMS320DM355

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数据表

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米6体育平台手机版_好二三四详情

DSP type

0

Operating system

Integrity, Linux, Neutrino, PrOS, Windows Embedded CE

Rating

Catalog

Operating temperature range (°C)

-40 to 100

DSP type

0

Operating system

Integrity, Linux, Neutrino, PrOS, Windows Embedded CE

Rating

Catalog

Operating temperature range (°C)

-40 to 100

NFBGA (ZCE)

337

169 mm² 13 x 13

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
High-Performance Digital Media System-on-Chip (DMSoC)
Up to 270-MHz ARM926EJ-S™ Clock Rate
MPEG4/JPEG Coprocessor Supports
- Up to 720p MPEG4 SP
- Up to 50M Pixels per Second JPEG
Video Processing Subsystem
- Hardware IPIPE for Real-Time Image Processing
- Up to 14-bit CCD/CMOS Digital Interface
- Histogram Module
- Resize Image 1/16x to 8x
- Hardware On-Screen Display
- Supports digital HDTV (720p/1080i) output for connection to external encoder
Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
Configurable Power-Saving Modes
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Extended Temperature 135- and 216-MHz Devices are Available
3.3-V and 1.8-V I/O, 1.3-V Core
Debug Interface Support
337-Pin Ball Grid Array at 65 nm Process Technology
High-Performance Digital Media System-on-Chip
- 135-, 216-, and 270-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9
- Extended Temperature support for 135- and 216-Mhz Devices are Available
ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT™ Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 8K-Byte ROM
- Little Endian
MPEG4/JPEG Coprocessor
- Fixed Function Coprocessor Supports:
  - MPEG4 SP Codec at HD (720p), D1, VGA, SIF
  - JPEG Codec up to 50M Pixels per Second
Video Processing Subsystem
- Front End Provides:
  - Hardware IPIPE for Real-Time Processing
  - up to 14-bit CCD/CMOS Digital Interface
  - 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
  - 10-/8-bit CCIR6565/BT655 Interface
  - Up to 75-MHz Pixel Clock
  - Histogram Module
  - Resize Engine
    - Resize Images From 1/16x to 8x
    - Separate Horizontal/Vertical Control
    - Two Simultaneous Output Paths
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Supports digital HDTV (720p/1080i) output for connection to external encoder
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 Full and High-Speed Device
- USB 2.0 Low, Full, and High-Speed Host
Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and CTS Flow Control)
Three Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I²C) Bus®
Two Audio Serial Port (ASP)
- I2S and TDM I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 24 MHz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
90nm Process Technology
3.3-V and 1.8-V I/O, 1.3-V Internal

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
High-Performance Digital Media System-on-Chip (DMSoC)
Up to 270-MHz ARM926EJ-S™ Clock Rate
MPEG4/JPEG Coprocessor Supports
- Up to 720p MPEG4 SP
- Up to 50M Pixels per Second JPEG
Video Processing Subsystem
- Hardware IPIPE for Real-Time Image Processing
- Up to 14-bit CCD/CMOS Digital Interface
- Histogram Module
- Resize Image 1/16x to 8x
- Hardware On-Screen Display
- Supports digital HDTV (720p/1080i) output for connection to external encoder
Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
Configurable Power-Saving Modes
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Extended Temperature 135- and 216-MHz Devices are Available
3.3-V and 1.8-V I/O, 1.3-V Core
Debug Interface Support
337-Pin Ball Grid Array at 65 nm Process Technology
High-Performance Digital Media System-on-Chip
- 135-, 216-, and 270-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9
- Extended Temperature support for 135- and 216-Mhz Devices are Available
ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT™ Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 8K-Byte ROM
- Little Endian
MPEG4/JPEG Coprocessor
- Fixed Function Coprocessor Supports:
  - MPEG4 SP Codec at HD (720p), D1, VGA, SIF
  - JPEG Codec up to 50M Pixels per Second
Video Processing Subsystem
- Front End Provides:
  - Hardware IPIPE for Real-Time Processing
  - up to 14-bit CCD/CMOS Digital Interface
  - 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
  - 10-/8-bit CCIR6565/BT655 Interface
  - Up to 75-MHz Pixel Clock
  - Histogram Module
  - Resize Engine
    - Resize Images From 1/16x to 8x
    - Separate Horizontal/Vertical Control
    - Two Simultaneous Output Paths
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Supports digital HDTV (720p/1080i) output for connection to external encoder
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 Full and High-Speed Device
- USB 2.0 Low, Full, and High-Speed Host
Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and CTS Flow Control)
Three Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I²C) Bus®
Two Audio Serial Port (ASP)
- I2S and TDM I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 24 MHz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
90nm Process Technology
3.3-V and 1.8-V I/O, 1.3-V Internal

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE)
A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

An inter-integrated circuit (I2C) Bus interface
Two audio serial ports (ASP)
Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
A 64-bit watchdog timer
Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
Three UARTs with hardware handshaking support on one UART
Three serial port Interfaces (SPI)
Four pulse width modulator (PWM) peripherals
Four real time out (RTO) outputs
Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
A USB 2.0 full and high-speed device and host interface
Two external memory interfaces:
- An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND.
- A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM355 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE)
A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

An inter-integrated circuit (I2C) Bus interface
Two audio serial ports (ASP)
Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
A 64-bit watchdog timer
Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
Three UARTs with hardware handshaking support on one UART
Three serial port Interfaces (SPI)
Four pulse width modulator (PWM) peripherals
Four real time out (RTO) outputs
Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
A USB 2.0 full and high-speed device and host interface
Two external memory interfaces:
- An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND.
- A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM355 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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	类型	标题		下载最新的英语版本		日期
*	数据表	TMS320DM355 Digital Media System-on-Chip (DMSoC) 数据表 (Rev. G)				2010年 6月 24日
*	勘误表	TMS320DM355 Digital Media System-on-Chip Silicon Errata (Revs 1.1, 1.3 and 1.4) (Rev. E)				2010年 6月 24日
	应用手册	高速接口布局指南 (Rev. J)	PDF \| HTML	英语版 (Rev.J)	PDF \| HTML	2023年 3月 23日
	用户指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)				2020年 6月 1日
	应用手册	构建小型嵌入式Linux 内核示例 (Rev. A)		英语版 (Rev.A)		2013年 7月 30日
	应用手册	Powering the TMS320DM335 and TMS320DM355 with the TPS650061				2011年 10月 13日
	应用手册	Migrating From TMS320DM35x to TMS320DM36x Devices (Rev. A)				2011年 6月 2日
	米6体育平台手机版_好二三四概述	Multi-Megapixel Reference Designs (Rev. A)				2011年 3月 22日
	应用手册	Migrating From TMS320DM355/335 Silicon Revision 1.1 to 1.3 or 1.4 (Rev. B)				2011年 1月 5日
	用户指南	TMS320DM35x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. B)				2010年 8月 25日
	用户指南	TMS320DM355 Digital Media System-on-Chip ARM Subsystem Reference Guide (Rev. A)				2010年 8月 4日
	应用手册	TMS320DM355 Power Consumption for Common Application Usage Scenarios (Rev. A)				2010年 7月 16日
	更多文献资料	TMS320DM3x DaVinci Video Processors				2010年 4月 11日
	应用手册	USB Compliance Checklist (Rev. A)				2010年 3月 10日
	应用手册	Implementing DDR2/mDDR PCB Layout on the TMS320DM35x DMSoC (Rev. D)				2009年 11月 11日
	应用手册	LSP 2.10 DaVinci Linux Drivers (Rev. A)				2009年 7月 8日
	更多文献资料	TMS320DM3x Highlights				2009年 3月 3日
	更多文献资料	Complimentary Analog Devices for DM355 Digital Media Processor				2009年 2月 17日
	用户指南	TMS320DM355 DVEVM v1.30 Getting Started Guide (Rev. B)				2008年 12月 31日
	用户指南	TMS320DM35x Digital Media System-on-Chip Video Processing Back End (VPBE) RG (Rev. C)				2008年 10月 16日
	应用手册	Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A)				2008年 8月 21日
	更多文献资料	达芬奇技术概述手册 (Rev. B)		英语版 (Rev.B)		2008年 8月 12日
	应用手册	TMS320DM355 DSP Power Reference Design PR742 (Rev. A)				2008年 8月 8日
	应用手册	Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)				2008年 7月 17日
	用户指南	TMS320DM35x Digital Media System-on-Chip Video Processing Front End (VPFE) RG (Rev. A)				2008年 6月 30日
	用户指南	TMS320DM35x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. B)				2008年 3月 18日
	用户指南	TMS320DM35x DMSoC Universal Serial Bus (USB) User's Guide (Rev. C)				2008年 3月 13日
	用户指南	TMS320DM355 DMSoC Peripherals Overview Reference Guide (Rev. A)				2007年 12月 7日
	用户指南	TMS320DM35x DMSoC Multimedia Card(MMC)/Secure Digital(SD)(SDIO) Card Controller (Rev. C)				2007年 11月 28日
	用户指南	TMS320DM35x DMSoC DDR2/mDDR Memory Controller Reference Guide (Rev. D)				2007年 11月 19日
	用户指南	TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. B)				2007年 10月 23日
	用户指南	TMS320DM35x DMSoC Enhanced DMA (EDMA) User's Guide (Rev. A)				2007年 10月 23日
	用户指南	TMS320DM35x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. B)				2007年 10月 16日
	更多文献资料	TMS320DM355 DaVinci FAQ (Rev. A)				2007年 9月 27日
	用户指南	TMS320DM35x Audio Serial Port (ASP) Reference Guide (Rev. C)				2007年 9月 4日
	用户指南	TMS320DM35x DMSoC Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A)				2007年 9月 4日
	用户指南	TMS320DM35x DMSoC Timer/Watchdog Timer User's Guide (Rev. A)				2007年 9月 4日
	用户指南	TMS320DM35x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. B)				2007年 9月 4日
	用户指南	TMS320DM35x Digital Media System-on-Chip Real Time Out (RTO) Reference Guide				2007年 9月 4日
	更多文献资料	DaVinci Newsletter - Fall 2007 Issue (Rev. B)				2007年 8月 14日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。与低成本的 XDS110 和高性能的 XDS560v2 相比，XDS200 在低成本和高性能之间实现了平衡；并在单个仓体中支持广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

TI.com 上无现货

调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的米6体育平台手机版_好二三四，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)

TI.com 上无现货

调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

TI.com 上无现货

软件开发套件 (SDK)

LINUXDVSDK-DV — Linux 数字视频软件开发套件 (DVSDK) v2x/v3x - 达芬奇数字媒体处理器

2010 年 10 月生效 - Linux DVSDK v4 已发布。对于上面未列出的 DaVinci™ 器件，请在 TI.com 上搜索您的器件型号；此米6体育平台手机版_好二三四页面将提供指向您当前 DVSDK 的链接。

借助 Linux™ 数字视频软件开发套件 (DVSDK)，DaVinci 系统集成人员能快速开发可在 DaVinci 系列不同器件间轻松移植的 Linux 多媒体应用。每个 DVSDK 都包含一套预先测试的操作系统、应用框架和具有示例程序的编解码器库，这些示例程序演示了从外设流入和流出音频和视频数据的实时解码和编码过程。对于配备 DSP 内核的 DaVinci 器件，DVSDK (...)

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应用软件和框架

TMDMFP — 多媒体框架米6体育平台手机版_好二三四 (MFP) - 编解码器引擎，框架组件和 xDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable DSPs over fixed-function devices is their ability to accelerate multiple multimedia functions in a single device. TI multimedia framework products are designed to enable users to easily share a DSP between algorithms by handling (...)

用户指南: PDF

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操作系统 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)

来源：Mentor Graphics Corporation

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