DMVA3
- High-Performance DaVinci Digital Media Processors
- Up to 970-MHz ARM® Cortex™-A8 RISC Processor
- Up to 1940 ARM Cortex-A8 MIPS
- ARM Cortex-A8 Core
- ARMv7 Architecture
- In-Order, Dual-Issue, Superscalar Processor Core
- NEON™ Multimedia Architecture
- Supports Integer and Floating Point
- Jazelle® RCT Execution Environment
- ARMv7 Architecture
- ARM Cortex-A8 Memory Architecture
- 32KB of Instruction and Data Caches
- 256KB of L2 Cache with ECC
- 64KB of RAM, 48KB of Boot ROM
- 256KB of On-Chip Memory Controller (OCMC) RAM
- Imaging Subsystem (ISS)
- Camera Sensor Connection
- Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
- CSI2 Serial Connection
- Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
- Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
- Image Pipe (IPIPE) for Real-Time Image and Video Processing
- Resizer
- Resizing Image and Video From 1/16x to 8x
- Generating Two Different Resizing Outputs Concurrently
- Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
- Camera Sensor Connection
- Vision Coprocessor
- Face Detect (FD) Engine
- Hardware Face Detection for up to 35 Faces Per Frame
- Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
- Encode, Decode, Transcode Operations
- H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
- Fourth-Generation Motion-Compensated Noise Filter
- Media Controller
- Controls the HDVPSS, HDVICP2, Vision Coprocessor, and ISS
- Endianness
- ARM Instructions and Data – Little Endian
- HD Video Processing Subsystem (HDVPSS)
- Two 165-MHz HD Video Capture Inputs
- One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
- One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
- Two 165-MHz HD Video Display Outputs
- One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
- Component HD Analog Output
- Composite Analog Output
- Digital HDMI 1.3 Transmitter with Integrated PHY
- Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
- Three Graphics Layers and Compositors
- Two 165-MHz HD Video Capture Inputs
- 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
- Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
- Up to Two x 16 Devices, 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
- Programmable Multi-Zone Memory Mapping
- Enables Efficient 2D Block Accesses
- Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
- General-Purpose Memory Controller (GPMC)
- 8- or 16-Bit Multiplexed Address and Data Bus
- 512MB of Total Address Space Divided Among up to 8 Chip Selects
- Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
- Enhanced Direct Memory Access (EDMA) Controller
- Four Transfer Controllers
- 64 Independent DMA Channels
- 8 QDMA Channels
- Ethernet Switch with Dual 10-, 100-, or
1000-Mbps External Interfaces (EMAC Software)- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII/RMII/GMII/RGMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
- Reset Isolation
- IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
- Dual USB 2.0 Ports with Integrated PHYs
- USB2.0 High- and Full-Speed Clients
- USB2.0 High-, Full-, and Low-Speed Hosts
- Supports End Points 0-15
- One PCI Express 2.0 Port with Integrated PHY
- Single Port with 1 Lane at 5.0 GT/s
- Configurable as Root Complex or Endpoint
- Eight 32-Bit General-Purpose Timers (Timer1–8)
- One System Watchdog Timer (WDT0)
- Three Configurable UART/IrDA/CIR Modules
- UART0 with Modem Control Signals
- Supports up to 3.6864 Mbps
- SIR, MIR, FIR (4.0 MBAUD), and CIR
- Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
- Each with Four Chip Selects
- Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
- Supporting up to 1-, 4-, or 8-Bit Modes
- Dual Controller Area Network (DCAN) Module
- CAN Version 2 Part A, B
- Four Inter-Integrated Circuit (I2C Bus™) Ports
- Two Multichannel Audio Serial Ports (McASP)
- Six Serializer Transmit and Receive Ports
- Two Serializer Transmit and Receive Ports
- DIT-Capable For S/PDIF (All Ports)
- Four Audio Tracking Logic (ATL) Modules
- One Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
- Direct Interface to 1 Hard Disk Drive
- Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Real-Time Clock (RTC)
- One-Time or Periodic Interrupt Generation
- Up to 125 General-Purpose I/O (GPIO) Pins
- One Spin Lock Module with up to 128 Hardware Semaphores
- One Mailbox Module with 12 Mailboxes
- On-Chip ARM ROM Bootloader (RBL)
- Power, Reset, and Clock Management
- SmartReflex™ Technology (Level 2b)
- Multiple Independent Core Power Domains
- Multiple Independent Core Voltage Domains
- Support for Two Operating Points (OPP120 and OPP100) per Voltage Domain
- Clock Enable and Disable Control for Subsystems and Peripherals
- 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
- IEEE 1149.1 (JTAG) Compatible
- 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
- 45-nm CMOS Technology
- 1.8- and 3.3-V Dual Voltage Buffers for General I/O
All trademarks are the property of their respective owners.
DMVA3 and DMVA4 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of multichannel Digital Video Recorders (DVR), Network Video Recorders (NVR), HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD and HD resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 or more than 8 channels of D1 real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DMVA3/4 are uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.
The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. In addition, the devices include a custom vision coprocessor with an available suite of TI-developed video analytics functions. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); a vision coprocessor; up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two Controller Area Network (DCAN) modules; one Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a Spin Lock; and Mailbox.
Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.
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技術資料
| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| * | エラッタ | DMVA3 and DMVA4 DaVinci Digital Media Processor SE (Silicon Rev. 1.1, 1.0) (Rev. A) | 2013年 12月 18日 | |||
| * | データシート | DMVA3 and DMVA4 DaVinci Digital Media Processor データシート (Rev. B) | 2013年 12月 18日 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点