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SN74CBT16811C

アクティブ

事前充電出力と –2V アンダーシュート保護機能搭載、5V、1:1 (SPST)、24 チャネル FET バス・スイッチ

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データシート

SN74CBT16811C

アクティブ
データシート ご注文はこちら

製品詳細

Configuration 1:1 SPST Number of channels 24 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 8 CON (typ) (pF) 15.5 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 24 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 8 CON (typ) (pF) 15.5 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
  • B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot-Plugging
  • Supports PCI Hot Plug
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
  • B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot-Plugging
  • Supports PCI Hot Plug
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

Widebus is a trademark of Texas Instruments.

The SN74CBT16811C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16811C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The SN74CBT16811C is organized as two 12-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE\ is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The B port is precharged to BIASV through the equivalent of a 10-k resistor when OE\ is high, or if the device is powered down (VCC = 0 V).

During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT16811C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16811C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The SN74CBT16811C is organized as two 12-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE\ is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The B port is precharged to BIASV through the equivalent of a 10-k resistor when OE\ is high, or if the device is powered down (VCC = 0 V).

During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート SN74CBT16811C データシート (Rev. C) 2003年 10月 15日
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セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
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シミュレーション・モデル

SN74CBT16811C IBIS Model (Rev. B)

SCDM019B.ZIP (27 KB) - IBIS Model
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