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TIDA-01021
适用于 DSO、雷达和 5G 无线测试仪的多通道 JESD204B 15GHz 时钟参考设计
TIDA-01021
概述
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency. By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described, guiding users through the part selection process and design optimization. Finally, schematic, board layout, hardware testing, and results are also presented.
特性
- Up to 15GHz sample clock generation
- Multi-channel JESD204B compliant clock solution
- Low phase noise clocking for RF sampling ADC/DAC
- Configurable phase synchronization to achieve low skew in multi-channel system
- Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)
我们开发的全面组装电路板仅用于测试和性能验证，不可用于销售。
设计文件和米6体育平台手机版_好二三四
设计文件
下载现成的系统文件，加快您的设计过程。
米6体育平台手机版_好二三四
在设计中包括 TI 米6体育平台手机版_好二三四和可能的替代米6体育平台手机版_好二三四。
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| 类型 | 标题 | 下载最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| 技术文章 | Step-by-step considerations for designing wide-bandwidth multichannel systems | PDF | HTML | 2019年 6月 4日 | |||
| 设计指南 | 适用于DSO、雷达和5G 无线测试仪的多通道JESD204B 15GHz 时钟参考设计 (Rev. A) | 英语版 (Rev.A) | 2017年 10月 24日 | |||
| 技术文章 | Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy | PDF | HTML | 2017年 8月 28日 |