12 Revision History
Changes from Revision E (October 2019) to Revision F (January 2024)
- 更新了整个文档中的表格、图和交叉参考的编号格式Go
- 将提到 I2C 的旧术语实例通篇更改为控制器和目标Go
- Changed Power supply ramp footnote in the Timing
Characteristics table Go
- Added additional details on VDD instability and instruction to set
recal bit to a '1' to recalibrate the PLLGo
- Updated references of chx_lvds_cmtrim_inc = 2 to chx_lvds_cmtrim_inc
= 0Go
Changes from Revision D (June 2019) to Revision E (October 2019)
- 删除了数据表中的分数输出分频器 (FOD) 和展频时钟 (SSC) 信息Go
- Added footnote to Timing Characteristics table Go
- Removed FOD from Functional Block Diagram
Go
- Changed REFSEL selection from L to H.Go
- Removed Output Channel Divider Types and Delay table Go
- Removed the FOD control bits in the Power Management graphicGo
- Added Page-mode EEPROM read instructionsGo
- Changed Pre-Configured EEPROM Page 0 graphicGo
- Changed Pre-Configured EEPROM Page 1 graphicGo
- Added additional details on pullup resistor and load capacitor added
to power-up sequenceGo
- Removed fractional output divider information from the registers Go
- Removed FOD information from the CDCI6214 Registers
tableGo
Changes from Revision C (November 2018) to Revision D (June 2019)
- Added VDDREF and tablenote to the output supply voltage parameter in the Recommended Operating Conditions
Go
- Added statement on chX_1p8vdet setting Go
- Changed CDCI6214 - Pre-Configured EEPROM Page 0 graphicGo
Changes from Revision B (April 2018) to Revision C (November 2018)
- Changed pin names for pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N.Go
- Changed descriptions for pins 1 and 2Go
- Changed pin names for pins 1 and 2 in
#GUID-FFC11261-A157-480F-A1A3-31A56ED88FB5/TITLE-SNAS690SNAS6908516_3
Go
- Changed pin names for pins 1 and 2 in
#GUID-FA6F37A7-22A5-4625-AB38-51BC5813B88F/TITLE-SNAS690SNAS6902663_4
Go
- Changed Input capacitance specification symbols in
#GUID-FA6F37A7-22A5-4625-AB38-51BC5813B88F/TITLE-SNAS690SNAS6902663_4
from: CIN_XOUT and CIN_XIN to: CIN_XOUT/FB_P and CIN_XIN/FB_P
Go
- Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Functional Block Diagram
Go
- Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Reference Block graphicGo
- Changed External (XIN) pin to: FB_P/N in the Phase-Locked Loop Circuit graphicGo
- Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the CDCI6214 - Pre-Configured EEPROM Page 0 and CDCI6214 - Pre-Configured EEPROM Page 1 graphicsGo
- Changed pins XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Typical Applications schematicsGo
- Changed design parameter superscript to a subscript Go
Changes from Revision * (July 2017) to Revision A (October 2017)
- 将器件状态从“预告信息”更改为“量产数据”Go
- Changed REFSEL pin description to reflext REFMUX control. Go