SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see Section 2.5.4.
Table 2-14 lists the memory-mapped registers for the NVIC. All register offset addresses not listed in Table 2-14 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x100 | EN0 | Interrupt 0-31 Set Enable | Section 2.4.1 |
| 0x104 | EN1 | Interrupt 32-63 Set Enable | Section 2.4.1 |
| 0x108 | EN2 | Interrupt 64-95 Set Enable | Section 2.4.1 |
| 0x10C | EN3 | Interrupt 96-113 Set Enable | Section 2.4.1 |
| 0x180 | DIS0 | Interrupt 0-31 Clear Enable | Section 2.4.2 |
| 0x184 | DIS1 | Interrupt 32-63 Clear Enable | Section 2.4.2 |
| 0x188 | DIS2 | Interrupt 64-95 Clear Enable | Section 2.4.2 |
| 0x18C | DIS3 | Interrupt 96-113 Clear Enable | Section 2.4.2 |
| 0x200 | PEND0 | Interrupt 0-31 Set Pending | Section 2.4.3 |
| 0x204 | PEND1 | Interrupt 32-63 Set Pending | Section 2.4.3 |
| 0x208 | PEND2 | Interrupt 64-95 Set Pending | Section 2.4.3 |
| 0x20C | PEND3 | Interrupt 96-113 Set Pending | Section 2.4.3 |
| 0x280 | UNPEND0 | Interrupt 0-31 Clear Pending | Section 2.4.4 |
| 0x284 | UNPEND1 | Interrupt 32-63 Clear Pending | Section 2.4.4 |
| 0x288 | UNPEND2 | Interrupt 64-95 Clear Pending | Section 2.4.4 |
| 0x28C | UNPEND3 | Interrupt 96-113 Clear Pending | Section 2.4.4 |
| 0x300 | ACTIVE0 | Interrupt 0-31 Active Bit | Section 2.4.5 |
| 0x304 | ACTIVE1 | Interrupt 32-63 Active Bit | Section 2.4.5 |
| 0x308 | ACTIVE2 | Interrupt 64-95 Active Bit | Section 2.4.5 |
| 0x30C | ACTIVE3 | Interrupt 96-127 Active Bit | Section 2.4.5 |
| 0x400 | PRI0 | Interrupt 0-3 Priority | Section 2.4.6 |
| 0x404 | PRI1 | Interrupt 4-7 Priority | Section 2.4.6 |
| 0x408 | PRI2 | Interrupt 8-11 Priority | Section 2.4.6 |
| 0x40C | PRI3 | Interrupt 12-15 Priority | Section 2.4.6 |
| 0x410 | PRI4 | Interrupt 16-19 Priority | Section 2.4.6 |
| 0x414 | PRI5 | Interrupt 20-23 Priority | Section 2.4.6 |
| 0x418 | PRI6 | Interrupt 24-27 Priority | Section 2.4.6 |
| 0x41C | PRI7 | Interrupt 28-31 Priority | Section 2.4.6 |
| 0x420 | PRI8 | Interrupt 32-35 Priority | Section 2.4.6 |
| 0x424 | PRI9 | Interrupt 36-39 Priority | Section 2.4.6 |
| 0x428 | PRI10 | Interrupt 40-43 Priority | Section 2.4.6 |
| 0x42C | PRI11 | Interrupt 44-47 Priority | Section 2.4.6 |
| 0x430 | PRI12 | Interrupt 48-51 Priority | Section 2.4.6 |
| 0x434 | PRI13 | Interrupt 52-55 Priority | Section 2.4.6 |
| 0x438 | PRI14 | Interrupt 56-59 Priority | Section 2.4.6 |
| 0x43C | PRI15 | Interrupt 60-63 Priority | Section 2.4.6 |
| 0x440 | PRI16 | Interrupt 64-67 Priority | Section 2.4.6 |
| 0x444 | PRI17 | Interrupt 68-71 Priority | Section 2.4.6 |
| 0x448 | PRI18 | Interrupt 72-75 Priority | Section 2.4.6 |
| 0x44C | PRI19 | Interrupt 76-79 Priority | Section 2.4.6 |
| 0x450 | PRI20 | Interrupt 80-83 Priority | Section 2.4.6 |
| 0x454 | PRI21 | Interrupt 84-87 Priority | Section 2.4.6 |
| 0x458 | PRI22 | Interrupt 88-91 Priority | Section 2.4.6 |
| 0x45C | PRI23 | Interrupt 92-95 Priority | Section 2.4.6 |
| 0x460 | PRI24 | Interrupt 96-99 Priority | Section 2.4.6 |
| 0x464 | PRI25 | Interrupt 100-103 Priority | Section 2.4.6 |
| 0x468 | PRI26 | Interrupt 104-107 Priority | Section 2.4.6 |
| 0x46C | PRI27 | Interrupt 108-111 Priority | Section 2.4.6 |
| 0x470 | PRI28 | Interrupt 112-113 Priority | Section 2.4.6 |
| 0xF00 | SWTRIG | Software Trigger Interrupt | Section 2.4.7 |
Complex bit access types are encoded to fit into small table cells. Table 2-15 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| WO | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |