SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 5-1 lists the memory-mapped registers for the processor support and exception module. All register offset addresses not listed in Table 5-1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | SYSEXCRIS | System Exception Raw Interrupt Status | Section 5.2.1 |
| 0x4 | SYSEXCIM | System Exception Interrupt Mask | Section 5.2.2 |
| 0x8 | SYSEXCMIS | System Exception Masked Interrupt Status | Section 5.2.3 |
| 0xC | SYSEXCIC | System Exception Interrupt Clear | Section 5.2.4 |
Complex bit access types are encoded to fit into small table cells. Table 5-2 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |