SWRZ073C May 2017 – May 2021 IWR1642
| Advisory Number | Advisory Title | IWR16xx | |
|---|---|---|---|
| ES1.0 | ES2.0 | ||
| Main Subsystem | |||
| MSS#10 | Partial Write After a Full Data Width Write Fails to Mailbox Memory if ECC is Enabled | X | |
| MSS#11 | Clock Monitoring Logic Core Clock Comparator (CCCB) for CPU Clock Cannot be Used | X | |
| MSS#12 | MCAN Filter Event Interrupt not Connected to DMA | X | |
| MSS#14 | Asynchronous Assertion of SoC Warm Reset may not Work Reliably When Device Operating on PLL Clock | X | |
| MSS#16 | Delay Time, ETM Trace Clock to ETM Data Valid does not Meet Datasheet Specification | X | |
| MSS#17 | Invalid Pre-fetch from MSS CR4 Processor (due to Speculative Read Operation from Tightly Coupled Memory Instance) Leads to Generation of MSS_ESM Group 3 Channel 7: MSS_TCMA_FATAL_ERR | X | X |
| MSS#18(1) | Core Compare Module (CCM-R4F) may Cause nERROR Toggle After First Reset De-assertion Subsequent to Power Application | X | X |
| MSS#19 | DMA Read from Unimplemented Address Space may Result in DMA Hang Scenario | X | X |
| MSS#20 | Radar Frame Stuck due to Missing Synchronizer Logic in Hardware | X | X |
| MSS#22 | CAN-FD: Message Transmitted With Wrong Arbitration and Control Fields | X | X |
| MSS#37B | DCC Module Frequency Comparison can Report Erroneous Results | X | X |
| MSS#38A | GPIO Glitch During Power-Up | X | X |
| MSS#39 | The state of the MSS DMA is left pending and uncleared on any DMA MPU fault | X | X |
| MSS#42 | DSP L2 memory initialisation can reoccur on execution DSP self test (STC) OR DSP Power cycling execution by application. | X | X |
| MSS#43A | Read-data from internal registers of PCR is not reliable. Shared PCS region protection is also not supported | X | X |
| MSS#44 | SYNC IN input pulse wider than 4usec can cause a FRC lockstep error | X | X |
| MSS#45 | Bootup failure during the serial flash busy state | X | X |
| Analog / Millimeter Wave | |||
| ANA#06 | Return Loss Measurement on TX: S11 < –9dB, RX S11 < –6.5dB (Accepted Value of < –10dB) | X | |
| ANA#08A | Doppler Spur Observed at Certain RF Frequencies | X | X |
| ANA#09A(1) | Synthesizer Frequency Nonlinearity around 76.8 GHz when Synthesizer (Chirp) Frequency Monitor Enabled | X | X |
| ANA#10A(1) | Unreliable Readings from Synthesizer Supply Voltage Monitor | X | X |
| ANA#11A | TX, RX Gain Calibrations Sensitive to Large External Interference | X | X |
| ANA#12A | Second Harmonic (HD2) Present in the Receiver | X | X |
| ANA#15 | Excessive TX-RX Coupling or Reflection can Lead to Saturated RX Output | X | X |
| ANA#16 | LVDS Coupling to Clock System | X | X |
| ANA#17A | On-Board Supply Ringing Induced Spur | X | X |
| ANA#18B | Spurs Caused due to Digital Activity Coupling to XTAL | X | X |
| ANA#20 | Occasional Failures Observed During Calibration of the Radar Subsystem | X | X |
| ANA#21A | Out of Band Radiated Spectral Emission | X | X |
| ANA#22A | Overshoot and Undershoot During Inter-Chirp Idle Time | X | X |
| ANA#24A | 40-MHz OSC CLKOUT Causing Spurs in 2D-FFT Spectrum | X | X |
| ANA#27 | Digital Temperature Sensor Having Higher Error | X | X |
| DSP Subsystem | |||
| DSS#01 | Access to L3 Region Above Allocated Region may Result in Double Bit ECC Error if ECC is Enabled | X | |
| DSS#02 | L1P Parity Error not Connected to ESM | X | |
| DSS#03 | Different Number of Chirps in ADC Buffer's Ping and Pong Memory is not Supported | X | |
| DSS#04 | Partial Write After Full Data Width Write Fails to HS RAM, ADC Buffer and Data Transfer Memory if ECC is Enabled for that Memory | X | |
| DSS#05 | Byte Writes not Supported to L3 If ECC is Enabled | X | |
| DSS#06 | Available L3 RAM for Customer Application is Lesser by 128KB | X | |
| DSS#07 | Temperature Sensor Located Near DSP not Working | X | |