SWRZ131B September 2022 – June 2024 CC1354R10
Table 1-1 lists all advisories, modules affected, and the applicable silicon revisions.
MODULE | DESCRIPTION | SILICON REVISIONS AFFECTED | |||
---|---|---|---|---|---|
C | |||||
Radio | Advisory Radio_01 — Proprietary radio modes: spurious emissions can affect regulatory compliance | Yes | |||
Radio | Advisory Radio_05 — Zigbee has a negative 3dB RSSI offset error with internal bias | Yes | |||
Power | Advisory Power_03 — Increased voltage ripple at low supply voltages when DC/DC converter is enabled. | Yes | |||
PKA | Advisory PKA_01 — Public key accelerator (PKA) interrupt line is always high when module is enabled and PKA is idle. | Yes | |||
PKA | Advisory PKA_02 — Public key accelerator (PKA) RAM is not byte accessible. | Yes | |||
I2C | Advisory I2C_01 — I2C module master status bit is set late. | Yes | |||
I2S | Advisory I2S_01 — I2S bus faults are not reported. | Yes | |||
CPU, System | Advisory CPU_Sys_01 — The SysTick calibration value (register field CPU_SCS.STCR.TENMS) used to set up 10-ms periodic ticks is incorrect when the system CPU is running off divided down 48MHz clock. | Yes | |||
CPU | Advisory CPU_04 — The Instrumentation Trace Macrocell (ITM) and Data Watchpoint and Trace (DWT) are active only if an external debug probe is attached to the JTAG port of the device. | Yes | |||
System | Advisory Sys_01 — Device might boot into ROM serial bootloader when waking up from shutdown | Yes | |||
System Controller | Advisory SYSCTRL_01 — Resets occurring in a specific 2MHz period during initial power up are incorrectly reported | Yes | |||
IO Controller | Advisory IOC_01 — Limited number of DIOs available for the bootloader backdoor | Yes | |||
ADC | Advisory ADC_02 — ADC samples can be delayed by two or 14 clock cycles (24MHz) when XOSC_HF is turned on or off, resulting in sample jitter. | Yes | |||
Flash | Advisory Flash_02 — Flash bank erase may timeout when operating at low temperatures with a low VDDS supply voltage. | Yes |