主页 电源管理 多通道 IC (PMIC)
主页
电源管理
多通道 IC (PMIC)

LP2996-N

正在供货

具有 DDR2 关断引脚的 1.5A DDR 终端稳压器

立即订购
数据表

LP2996-N

正在供货
数据表 立即订购

米6体育平台手机版_好二三四详情

Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR, DDR2
Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR, DDR2
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6 WQFN (NHP) 16 16 mm² 4 x 4
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.
filter 查找其他 多通道 IC (PMIC)
下载 观看带字幕的视频 视频

技术文档

star =有关此米6体育平台手机版_好二三四的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 3
类型 标题 下载最新的英语版本 日期
* 数据表 LP2996-N, LP2996A DDR Termination Regulator 数据表 (Rev. K) PDF | HTML 2016年 12月 23日
应用手册 Limiting DDR Termination Regulators’ Inrush Current 2016年 8月 23日
EVM 用户指南 AN-1268 LP2996 Evaluation Board (Rev. A) 2013年 5月 7日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

LP2996LQEVAL — DDR 终止稳压器

LP2996 DDR Termination Regulator

用户指南: PDF
TI.com 上无现货
仿真模型

LP2996-N PSpice Transient Model

SNOM563.ZIP (82 KB) - PSpice Model
下载
仿真模型

LP2996-N Unencrypted PSpice Transient Model

SNOM566.ZIP (7 KB) - PSpice Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
HSOIC (DDA) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
WQFN (NHP) 16 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

推荐米6体育平台手机版_好二三四可能包含与 TI 此米6体育平台手机版_好二三四相关的参数、评估模块或参考设计。

支持和培训

视频