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基于 Arm 的处理器

TMS320DM8127

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DaVinci 数字媒体处理器

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TMS320DM8127

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数据表 立即订购

米6体育平台手机版_好二三四详情

Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 1000 CPU 32-bit Display type 2 LCD Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators Face Detect Rating Catalog Power supply solution TPS65050 Operating temperature range (°C) -40 to 90
Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 1000 CPU 32-bit Display type 2 LCD Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators Face Detect Rating Catalog Power supply solution TPS65050 Operating temperature range (°C) -40 to 90
FCBGA (CYE) 684 529 mm² 23 x 23
  • High-Performance DaVinci Video Processors
    • Up to 1-GHz ARM® Cortex®-A8 RISC Core
    • Up to 750-MHz C674x VLIW DSP
    • Up to 6000 MIPS and 4500 MFLOPS
    • Fully Software-Compatible with C67x+, C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • Neon™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache
    • 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD)
    • Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS and ISS
  • Endianness
    • ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • One 165-MHz HD Video Capture Input
      • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
    • Composite or S-Video Analog Output
    • Macrovision® Support Available
    • Digital HDMI 1.3 Transmitter With Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, Rate Conversion
    • Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1066
    • Up to Eight x 8 Devices Total 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
    • Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY
    • Single Port With One Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules
    • UART0 With Modem Control Signals
    • Supports up to 3.6864 Mbps UART0/1/2
    • Supports up to 12 Mbps UART3/4/5
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to
    48 MHz)
    • Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to
    48 MHz)
    • Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs)
    • Dual Ten Serializer Transmit and Receive Ports
    • Quad Four Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer (ETB) and
    5-Pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
  • 45-nm CMOS Technology

    •  
  • High-Performance DaVinci Video Processors
    • Up to 1-GHz ARM® Cortex®-A8 RISC Core
    • Up to 750-MHz C674x VLIW DSP
    • Up to 6000 MIPS and 4500 MFLOPS
    • Fully Software-Compatible with C67x+, C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • Neon™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache
    • 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD)
    • Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS and ISS
  • Endianness
    • ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • One 165-MHz HD Video Capture Input
      • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
    • Composite or S-Video Analog Output
    • Macrovision® Support Available
    • Digital HDMI 1.3 Transmitter With Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, Rate Conversion
    • Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1066
    • Up to Eight x 8 Devices Total 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
    • Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY
    • Single Port With One Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules
    • UART0 With Modem Control Signals
    • Supports up to 3.6864 Mbps UART0/1/2
    • Supports up to 12 Mbps UART3/4/5
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to
    48 MHz)
    • Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to
    48 MHz)
    • Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs)
    • Dual Ten Serializer Transmit and Receive Ports
    • Quad Four Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer (ETB) and
    5-Pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
  • 45-nm CMOS Technology

    •  

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox

The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox

The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip
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通过第三方获得支持

TI 不会为该米6体育平台手机版_好二三四提供持续且直接的设计支持。要在设计期间获得支持，您可以联系以下某个第三方：D3 Engineering、elnfochips、Ittiam Systems、Path Partner Technology 或 Z3 Technologies。

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320DM812x DaVinci Video Processors 数据表 (Rev. C) 2014年 3月 25日
* 勘误表 TMS320DM8127 DaVinci™ Video Processors Errata (Silicon Revs 3.0, 2.1) (Rev. C) 2014年 3月 25日
* 用户指南 TMS320DM8127 and TMS320DM814x DaVinci™ Digital Media Processors TRM (Rev. G) 2016年 6月 30日
应用手册 高速接口布局指南 (Rev. J) PDF | HTML 英语版 (Rev.J) PDF | HTML 2023年 3月 23日
更多文献资料 TMDSCSK8127 Quick Start Guide 2017年 1月 5日
白皮书 针对支持视频功能航拍无人机的低延迟设计注意事项_China 英语版 2016年 11月 2日
用户指南 DM38x and TMS320DM8127 DaVinci™ Face Detect User's Guide (Rev. A) 2016年 6月 30日
用户指南 DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) User's Guide (Rev. A) 2016年 6月 30日
应用手册 Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 2013年 7月 19日
更多文献资料 DM81x Design Network Partners 2012年 6月 5日
应用手册 TI814x-DDR3-Init-U-Boot 2011年 10月 31日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
米6体育平台手机版_好二三四概述 DaVinci DM8168 and DM8148 Product Bulletin 2011年 3月 1日
米6体育平台手机版_好二三四概述 Software Makes Development Easy for DM8168 and DM8148 2011年 3月 1日
米6体育平台手机版_好二三四概述 Video Analytics on TI's Davinci Digital Media Processors Backgrounder 2011年 3月 1日
白皮书 C6Accel Whitepaper 2010年 9月 22日
用户指南 TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 2010年 7月 30日
应用手册 Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB 2009年 11月 25日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

Z3-3P-VIDEO-EVMS — Z3 技术处理器视频评估模块

Z3 专为 TI 的 DaVinci 和 AM57x 处理器开发了开源软件架构并提供支持。米6体育平台手机版_好二三四包括以多媒体为中心的框架、外设驱动程序、生产模块和完整的米6体育平台手机版_好二三四设计服务。Z3 还为有线和无线媒体米6体育平台手机版_好二三四提供了系统级设计和集成。

如需了解有关 Z3 Technology 的更多信息，请访问 http://z3technology.com。

来源：Z3 Technology
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调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。与低成本的 XDS110 和高性能的 XDS560v2 相比，XDS200 在低成本和高性能之间实现了平衡；并在单个仓体中支持广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的米6体育平台手机版_好二三四，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

TI.com 上无现货
软件开发套件 (SDK)

LINUXEZSDK-DAVINCI — 适用于 DM814x 和 DM816x 的 Linux EZ 软件开发套件 (EZSDK) - ALPHA 版

The Linux EZ Software Development Kit (EZ SDK) allows customers to evaluate their devices in minutes and begin development in less than an hour. This kit provides everything DaVinci™ developers need to evaluate and start developing on the DaVinci™ DM816x/DM814x processors. With the (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
TMS320DM8127 — DaVinci 数字媒体处理器 TMS320DM8147 — DaVinci 数字媒体处理器 TMS320DM8148 — DaVinci 数字媒体处理器
数字信号处理器 (DSP)
TMS320DM8165 — DaVinci 数字媒体处理器 TMS320DM8167 — DaVinci 数字媒体处理器 TMS320DM8168 — DaVinci 数字媒体处理器
下载选项
驱动程序或库

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
OMAPL137-HT — 高温低功耗 C674x 浮点 DSP + Arm 处理器 - 高达 456MHz OMAPL138B-EP — 345MHz 低功耗 C674x 浮点 DSP + ARM9 处理器（增强型米6体育平台手机版_好二三四） TMS320DM8127 — DaVinci 数字媒体处理器
数字信号处理器 (DSP)
SM320C6201-EP — 增强型米6体育平台手机版_好二三四 C6201 定点 DSP SM320C6415-EP — C6415 定点 DSP（增强型米6体育平台手机版_好二三四） SM320C6424-EP — C6424 定点 DSP（增强型米6体育平台手机版_好二三四） SM320C6455-EP — 增强型米6体育平台手机版_好二三四 C6455 定点 DSP SM320C6472-HIREL — 高可靠性米6体育平台手机版_好二三四 6 核 C6472 定点 DSP SM320C6678-HIREL — 高可靠性米6体育平台手机版_好二三四高性能 8 核 C6678 定点和浮点 DSP SM320C6701 — 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP — 增强型米6体育平台手机版_好二三四 C6701 浮点 DSP SM320C6711D-EP — C6711D 浮点 DSP（增强型米6体育平台手机版_好二三四） SM320C6712D-EP — C6712D DSP（增强型米6体育平台手机版_好二三四） SM320C6713B-EP — C6713 浮点 DSP（增强型米6体育平台手机版_好二三四） SM320C6727B — 军用级 C6727B 浮点 DSP SM320C6727B-EP — C6727 浮点 DSP（增强型米6体育平台手机版_好二三四） SMJ320C6201B — 军用定点数字信号处理器 SMJ320C6203 — 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 — 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP — 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP — 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C6202B — C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B — C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 — 定点数字信号处理器 TMS320C6205 — 定点数字信号处理器 TMS320C6211B — C62x 定点 DSP- 高达 167MHz TMS320C6421Q — C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q — C64x+ 定点 DSP - 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6452 — C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网 TMS320C6454 — C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 — C64x+ 频率高达 1.2GHz、具有 64 位 EMIFA、32 位和 16 位 DDR2、1Gbps 以太网的定点 DSP TMS320C6457 — 通信基础设施数字信号处理器 TMS320C6701 — C67x 浮点 DSP - 高达 167MHz、McBSP TMS320C6711D — C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D — C67x 浮点 DSP - 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 — C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B — C67x 浮点 DSP - 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B — C67x 浮点 DSP - 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 — C67x 浮点 DSP - 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B — C67x 浮点 DSP - 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 — 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 — 低功耗 C674x 浮点 DSP- 456MHz、PBGA
下载
驱动程序或库

C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
OMAPL137-HT — 高温低功耗 C674x 浮点 DSP + Arm 处理器 - 高达 456MHz OMAPL138B-EP — 345MHz 低功耗 C674x 浮点 DSP + ARM9 处理器（增强型米6体育平台手机版_好二三四） TMS320DM8127 — DaVinci 数字媒体处理器
数字信号处理器 (DSP)
SM320C6201-EP — 增强型米6体育平台手机版_好二三四 C6201 定点 DSP SM320C6415-EP — C6415 定点 DSP（增强型米6体育平台手机版_好二三四） SM320C6424-EP — C6424 定点 DSP（增强型米6体育平台手机版_好二三四） SM320C6455-EP — 增强型米6体育平台手机版_好二三四 C6455 定点 DSP SM320C6472-HIREL — 高可靠性米6体育平台手机版_好二三四 6 核 C6472 定点 DSP SM320C6678-HIREL — 高可靠性米6体育平台手机版_好二三四高性能 8 核 C6678 定点和浮点 DSP SM320C6701 — 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP — 增强型米6体育平台手机版_好二三四 C6701 浮点 DSP SM320C6711D-EP — C6711D 浮点 DSP（增强型米6体育平台手机版_好二三四） SM320C6712D-EP — C6712D DSP（增强型米6体育平台手机版_好二三四） SM320C6713B-EP — C6713 浮点 DSP（增强型米6体育平台手机版_好二三四） SM320C6727B — 军用级 C6727B 浮点 DSP SM320C6727B-EP — C6727 浮点 DSP（增强型米6体育平台手机版_好二三四） SMJ320C6201B — 军用定点数字信号处理器 SMJ320C6203 — 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 — 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP — 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP — 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C6202B — C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B — C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 — 定点数字信号处理器 TMS320C6205 — 定点数字信号处理器 TMS320C6211B — C62x 定点 DSP- 高达 167MHz TMS320C6421Q — C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q — C64x+ 定点 DSP - 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6452 — C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网 TMS320C6454 — C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 — C64x+ 频率高达 1.2GHz、具有 64 位 EMIFA、32 位和 16 位 DDR2、1Gbps 以太网的定点 DSP TMS320C6457 — 通信基础设施数字信号处理器 TMS320C6701 — C67x 浮点 DSP - 高达 167MHz、McBSP TMS320C6711D — C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D — C67x 浮点 DSP - 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 — C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B — C67x 浮点 DSP - 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B — C67x 浮点 DSP - 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 — C67x 浮点 DSP - 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B — C67x 浮点 DSP - 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 — 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 — 低功耗 C674x 浮点 DSP- 456MHz、PBGA
下载
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

此设计资源支持这些类别中的大部分米6体育平台手机版_好二三四。

查看米6体育平台手机版_好二三四详情页，验证是否能提供支持。
启动 下载选项
仿真模型

DM814x, DM8127 CYE BSDL Model (Rev. A)

SPRM550A.ZIP (16 KB) - BSDL Model
下载
仿真模型

DM814x, DM8127 CYE IBIS Model, Revision 2.01 (Rev. A)

SPRM555A.ZIP (3890 KB) - IBIS Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
FCBGA (CYE) 684 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

推荐米6体育平台手机版_好二三四可能包含与 TI 此米6体育平台手机版_好二三四相关的参数、评估模块或参考设计。

支持和培训

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