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CDCLVD1213

ACTIVE

Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider

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Data sheet

CDCLVD1213

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 20 Features 1:4 fanout, Selectable divider, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 20 Features 1:4 fanout, Selectable divider, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • 1:4 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Selectable Divider Ratio 1, /2, /4
  • Universal Input Accepts LVDS, LVPECL, and CML
  • 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking
  • 1:4 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Selectable Divider Ratio 1, /2, /4
  • Universal Input Accepts LVDS, LVPECL, and CML
  • 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML.

The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2, or 4.

The CDCLVD1213 is specifically designed for driving 50-Ω transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1213 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML.

The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2, or 4.

The CDCLVD1213 is specifically designed for driving 50-Ω transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1213 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.
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Technical documentation

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Type Title Date
* Data sheet CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer With Divider datasheet (Rev. A) PDF | HTML 31 Oct 2016
User guide Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM 12 Jul 2010

Design & development

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Simulation model

CDCLVD1213 IBIS Model (Rev. A)

SLLM087A.ZIP (14 KB) - IBIS Model
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