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CDCLVP111-EP

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HiRel, 1:10 LVPECL buffer with selectable input

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Data sheet

CDCLVP111-EP

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:10 fanout Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Output type LVPECL Input type CML, LVDS, LVPECL, SSTL
Function Differential Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:10 fanout Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Output type LVPECL Input type CML, LVDS, LVPECL, SSTL
LQFP (VF) 32 81 mm² 9 x 9
  • Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
  • Fully Compatible With LVECL and LVPECL
  • Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
    • Additive Jitter Less Than 1 ps
    • Propagation Delay Less Than 355 ps
    • Open Input Default State
    • LVDS, CML, SSTL input compatible
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111
  • Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
  • Fully Compatible With LVECL and LVPECL
  • Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
    • Additive Jitter Less Than 1 ps
    • Propagation Delay Less Than 355 ps
    • Open Input Default State
    • LVDS, CML, SSTL input compatible
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 is characterized for operation from –55°C to 125°C.

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 is characterized for operation from –55°C to 125°C.
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Type Title Date
* Data sheet Low-Voltage 1:10 LVPECL with Selectable Input Clock Driver.. datasheet 14 Dec 2012
* VID CDCLVP111-EP VID V6212624 21 Jun 2016

Design & development

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Simulation model

CDCLVP111 IBIS Model Version 2.0 (Rev. B)

SLLM052B.ZIP (35 KB) - IBIS Model
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Supported products & hardware

Supported products & hardware

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Evaluation board
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Software
Application software & framework
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IDE, configuration, compiler or debugger
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Support software
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