The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5-ns timing accuracy (class D).
The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.
APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 312.5 MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.
Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero delay and phase buildout may be enabled to control the phase relationship from input to outputs.
The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5-ns timing accuracy (class D).
The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.
APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 312.5 MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.
Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero delay and phase buildout may be enabled to control the phase relationship from input to outputs.
The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.