ZHCS266F June 2011 – May 2017 TRF7960A
PRODUCTION DATA.
Table 6-15 lists the registers available in the TRF7960A. These registers are described in the following sections.
| ADDRESS (hex) | REGISTER | READ/WRITE | SECTION |
|---|---|---|---|
| Main Control Registers | |||
| 0x00 | Chip Status Control | R/W | Section 6.14.1.1.1 |
| 0x01 | ISO Control | R/W | Section 6.14.1.1.2 |
| Protocol Subsetting Registers | |||
| 0x02 | ISO14443B TX Options | R/W | Section 6.14.1.2.1 |
| 0x03 | ISO14443A High-Bit-Rate Options | R/W | Section 6.14.1.2.2 |
| 0x04 | TX Timer Setting, H-byte | R/W | Section 6.14.1.2.3 |
| 0x05 | TX Timer Setting, L-byte | R/W | Section 6.14.1.2.4 |
| 0x06 | TX Pulse-Length Control | R/W | Section 6.14.1.2.5 |
| 0x07 | RX No Response Wait | R/W | Section 6.14.1.2.6 |
| 0x08 | RX Wait Time | R/W | Section 6.14.1.2.7 |
| 0x09 | Modulator and SYS_CLK Control | R/W | Section 6.14.1.2.8 |
| 0x0A | RX Special Setting | R/W | Section 6.14.1.2.9 |
| 0x0B | Regulator and I/O Control | R/W | Section 6.14.1.2.10 |
| Status Registers | |||
| 0x0C | IRQ Status | R | Section 6.14.1.3.1 |
| 0x0D | Collision Position and Interrupt Mask Register | R/W | Section 6.14.1.3.2 |
| 0x0E | Collision Position | R | Section 6.14.1.3.2 |
| 0x0F | RSSI Levels and Oscillator Status | R | Section 6.14.1.3.3 |
| FIFO Registers | |||
| 0x1A | Test | R/W | Section 6.14.1.4.1 |
| 0x1B | Test | R/W | Section 6.14.1.4.2 |
| 0x1C | FIFO Status | R | Section 6.14.1.5.1 |
| 0x1D | TX Length Byte1 | R/W | Section 6.14.1.5.2 |
| 0x1E | TX Length Byte2 | R/W | Section 6.14.1.5.2 |
| 0x1F | FIFO I/O Register | R/W | |