SPRZ457H January 2021 – December 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 2-3 lists all usage notes and the applicable silicon revision(s). Table 1-2 lists all advisories, modules affected, and the applicable silicon revision(s).
ID | DESCRIPTION | SILICON REVISIONS AFFECTED | |
---|---|---|---|
AM64x/AM243x 1.0 | AM64x/AM243x 2.0 | ||
Package | i2287 — Package Pin Assignment Difference between SR1.0 and SR2.0 | YES | YES |
OSPI | i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash | YES | YES |
MODULE | DESCRIPTION | SILICON REVISIONS AFFECTED | |
---|---|---|---|
AM64x/AM243x 1.0 | AM64x/AM243x 2.0 | ||
Boot | i2328 — Boot: USB MSC boots intermittently | YES | YES |
Boot | i2257 — xSPI boot mode redundant image boot failure | YES | NO |
Boot | i2307 — Boot: ROM does not properly select OSPI clocking modes based on BOOTMODE | YES | YES |
Boot | i2306 — Boot: ROM does not turn off internal termination resistors in SERDES | YES | NO |
Boot | i2363 — Boot: Peak voltage transitions may exceed PCIe spec during PCIe boot | YES | YES |
Boot | i2366— Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operation | YES | YES |
Boot | i2371— Boot: ROM code may hang in UART boot mode during data transfer | YES | YES |
CBASS | i2207 — CBASS: Command Arbitration Blocking | YES | YES |
CBASS | i2235 — CBASS Null Error Interrupt Not Masked By Enable Register | YES | YES |
CPSW | i2184 — CPSW: IET express traffic policing issue | YES | YES |
CPSW | i2185 — CPSW: Policer color marking issue | YES | YES |
CPSW | i2208 — CPSW: ALE IET Express Packet Drops | YES | YES |
CPSW | i2331 — CPSW: Device lockup when reading CPSW registers | YES | YES |
CPSW | i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up | YES | YES |
DebugSS | i2317 — Debug is not available after TRST pin de-assertion when device pin EMU1 is repurposed as MCU_OBSCLK0 | YES | NO |
DEBUG | i2283 — Restrictions on how CP Tracer Debug Probes can be used | YES | YES |
DDR | i2232 — DDR: Controller postpones more than allowed refreshes after frequency change | YES | YES |
DDR | i2244 — DDR: Valid stop value must be defined for write DQ VREF training | YES | YES |
DDR | i2259 — DDR: Possibility of starvation of low priority commands | YES | YES |
DDR | i2274 — DDR: Including DDR in BSCAN causes current alarm on the DDR supply | YES | NO |
DMA | i2285 — BCDMA: Blockcopy Gets Corrupted if TR Read Responses Interleave with Source Data Fetch | YES | NO |
DMA | i2320 — BCDMA and PKTDMA: Descriptors and TRs required to be returned unfragmented | YES | NO |
DMSC | i2245 — DMSC: Firewall Region requires specific configuration | YES | YES |
ECC_AGGR | i2049 — ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending ECC Aggregator Interrupts | YES | YES |
GPMC | i2313 — GPMC: Sub-32-bit read issue with NAND and FPGA/FIFO | YES | NO |
Internal Diagnostic Modules | i2103 — Incorrect Reporting of ECC_GRP, ECC_BIT and ECC_TYPE Information for Functional Safety Errors | YES | YES |
Interrupt Aggregator | i2196 — IA: Potential deadlock scenarios in IA | YES | YES |
ICSSG | i2305 — ICSSG: PRU RAM WRT during active FDB lookup write data corruption | YES | YES |
ICSSG | i2368 — ICSSG: Device lockup when reading registers in ICSSG module | YES | YES |
JTAG | i2228 — JTAG: TAP used by Debuggers may be inaccessible if TRSTn device pin is never asserted | YES | NO |
MCAN | i2279 — MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID | YES | YES |
MCAN | i2278 — MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID | YES | YES |
MDIO | i2329 — MDIO: MDIO interface corruption (CPSW and PRU-ICSS) | YES | YES |
MMCSD | i2312 — MMCSD: HS200 and SDR104 Command Timeout Window Too Small | YES | YES |
OSPI | i2189 — OSPI: Controller PHY Tuning Algorithm | YES | YES |
OSPI | i2303 — OSPI: OSPI0_LBCLK0 pin has input floating by default | YES | NO |
OSPI | i2249 — OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable | YES | YES |
OSPI | i2383 — OSPI: 2-byte address is not supported in PHY DDR mode | YES | YES |
PCIe | i2236 — PCIe: SERDES output reference clock cannot be used | YES | NO |
PCIe | i2241 — PCIe: The SerDes PCIe Reference Clock Output can exceed the 5.0 GT/s Data Rate RMS jitter limit | YES | NO |
PCIe | i2256 — PCIe: MSI or MSI-X does not trigger interrupt if address is not aligned to 8-bytes | YES | NO |
PCIe | i2243 — PCIe: Timing requirement for disabling output refclk during L1.2 substate is not met | YES | YES |
PCIe | i2326 — PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limits | YES | YES |
POK | i2277 — POK: De-Glitch (filter) is based upon only two samples | YES | NO |
PRG | i2253 — PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure | YES | YES |
PSIL | i2138— PSIL: Configuration accesses and source thread teardowns may cause data corruption | YES | YES |
RAT | i2062 — RAT: Error Interrupt Triggered Even When Error Logging Disable Is Set | YES | YES |
USART | i2310 — USART: Erroneous clear/trigger of timeout interrupt | YES | YES |
USART | i2311 — USART: Spurious DMA Interrupts | YES | YES |
USB | i2091 — USB: USB 2.0 PHY hangs if received signal amplitude crosses squelch threshold multiple times within the same packet | YES | NO |
USB | i2134 — USB: USB 2.0 Compliance Receive Sensitivity Test Limitation | YES | NO |
USB | i2409 — USB: USB2 PHY locks up due to short suspend | YES | YES |