ADS6445-EP
- Maximum Sample Rate: 125 MSPS
- 14-Bit Resolution with No Missing Codes
- Simultaneous Sample and Hold
- 3.5-dB Coarse Gain and up to 6-dB Programmable
Fine Gain for SFDR/SNR Trade-Off - Serialized LVDS Outputs with Programmable
Internal Termination Option - Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude Down to 400 mVPP - Internal Reference with External Reference Support
- No External Decoupling Required for References
- 3.3-V Analog and Digital Supply
- 64-pin QFN Package (9 mm × 9 mm)
- Feature Compatible Dual Channel Family
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS 数据表 (Rev. C) | 2013年 5月 29日 | |||
* | 辐射与可靠性报告 | ADS6445MRGCTEP Reliability Report | 2014年 12月 22日 | |||
应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010年 9月 10日 | ||||
应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009年 4月 28日 | ||||
应用手册 | 所选封装材料的热学和电学性质 | 2008年 10月 16日 | ||||
应用手册 | 模数规格和性能特性术语表 (Rev. A) | 最新英语版本 (Rev.B) | 2008年 10月 16日 | |||
应用手册 | 高速数据转换 | 英语版 | 2008年 10月 16日 | |||
应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008年 9月 4日 | ||||
应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||||
应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 | ||||
应用手册 | QFN Layout Guidelines | 2006年 7月 28日 |
设计和开发
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封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
VQFN (RGC) | 64 | Ultra Librarian |
订购和质量
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