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ロジックと電圧変換
電圧変換機能と電圧レベル・シフタ
固定方向電圧レベル・シフタ

CD40109B-MIL

アクティブ

CMOS クワッド、低電圧から高電圧へのレベル・シフタ (20V 定格)

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データシート

CD40109B-MIL

アクティブ
データシート ご注文はこちら

製品詳細

Technology family CD4000 Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 3 High input voltage (max) (V) 18 Vout (min) (V) 1385 Vout (max) (V) 18 Data rate (max) (Mbps) 24 IOH (max) (mA) -6.8 IOL (max) (mA) -6.8 Supply current (max) (µA) 18 Features 135.3552 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Military Operating temperature range (°C) -55 to 125
Technology family CD4000 Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 3 High input voltage (max) (V) 18 Vout (min) (V) 1385 Vout (max) (V) 18 Data rate (max) (Mbps) 24 IOH (max) (mA) -6.8 IOL (max) (mA) -6.8 Supply current (max) (µA) 18 Features 135.3552 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
  • Up and down level-shifting capability
  • Three-state outputs with separate enable controls
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range):
       = 1 V at VCC = 5 V, VDD = 10 V
       = 2 V at VCC = 10 V, VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
    • Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations

Data sheet acquired from Harris Semiconductor
  • Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
  • Up and down level-shifting capability
  • Three-state outputs with separate enable controls
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range):
       = 1 V at VCC = 5 V, VDD = 10 V
       = 2 V at VCC = 10 V, VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
    • Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations

Data sheet acquired from Harris Semiconductor

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート CD40109B TYPES データシート (Rev. B) 2003年 1月 15日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点

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