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SN74LV541AT

アクティブ

TTL 互換 CMOS 入力、3 ステート出力、8 チャネル、4.5V ～ 5.5V バッファ

ご注文はこちら
データシート

SN74LV541AT

アクティブ
データシート ご注文はこちら

製品詳細

Technology family LV-AT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-AT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 15.75 mm² 4.5 x 3.5
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Typical tpd of 4 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 5 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Typical tpd of 4 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 5 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74LV541AT is designed for 4.5-V to 5.5-V VCC operation. The inputs are TTL-voltage compatible, which allows them to be interfaced with bipolar outputs and 3.3-V devices. The device also can be used to translate from 3.3 V to 5 V.

This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

The 3-state control gate is a two-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV541AT is designed for 4.5-V to 5.5-V VCC operation. The inputs are TTL-voltage compatible, which allows them to be interfaced with bipolar outputs and 3.3-V devices. The device also can be used to translate from 3.3 V to 5 V.

This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

The 3-state control gate is a two-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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* データシート SN74LV541AT データシート (Rev. B) 2013年 7月 17日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点

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