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LMK61PD0A2

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±50 ppm, ultra-low jitter, pin selectable, differential oscillator

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Data sheet

LMK61PD0A2

ACTIVE
Data sheet Order now

Product details

Output frequency (MHz) 312.5 Output type HCSL, LVDS, LVPECL Stability (ppm) 50 Supply voltage (V) 3.3 Jitter (ps) 0.1 Operating temperature range (°C) -40 to 85
Output frequency (MHz) 312.5 Output type HCSL, LVDS, LVPECL Stability (ppm) 50 Supply voltage (V) 3.3 Jitter (ps) 0.1 Operating temperature range (°C) -40 to 85
QFM (SIA) 8 12.25 mm² 3.5 x 3.5
  • Ultra-low Noise, High Performance
    • Jitter: 90 fs RMS typical fOUT > 100 MHz
    • PSRR: –70 dBc, robust supply noise immunity
  • Flexible Output Frequency and Format; User
    Selectable
    • Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz,
      125 MHz, 156.25 MHz, 212.5 MHz,
      312.5 MHz
    • Formats: LVPECL, LVDS or HCSL
  • Total frequency tolerance of ± 50 ppm
  • Internal memory stores multiple start-up
    configurations, selectable through pin control
  • 3.3V operating voltage
  • Industrial temperature range (–40ºC to +85ºC)
  • 7 mm × 5 mm 8-pin package
  • Ultra-low Noise, High Performance
    • Jitter: 90 fs RMS typical fOUT > 100 MHz
    • PSRR: –70 dBc, robust supply noise immunity
  • Flexible Output Frequency and Format; User
    Selectable
    • Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz,
      125 MHz, 156.25 MHz, 212.5 MHz,
      312.5 MHz
    • Formats: LVPECL, LVDS or HCSL
  • Total frequency tolerance of ± 50 ppm
  • Internal memory stores multiple start-up
    configurations, selectable through pin control
  • 3.3V operating voltage
  • Industrial temperature range (–40ºC to +85ºC)
  • 7 mm × 5 mm 8-pin package

The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.

The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
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* Data sheet LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator datasheet (Rev. A) PDF | HTML 03 Nov 2015
EVM User's guide LMK61PDEVM User's Guide (Rev. A) 20 Nov 2015

Design & development

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Evaluation board

LMK61PDEVM — LMK61PDEVM Ultra-Low-Jitter Pin Selectable Oscillator EVM

The LMK61PDEVM evaluation modules provides a complete platform to evaluate the 100-fs RMS jitter performance and configurability of the Texas Instruments LMK61PD Ultra-Low Jitter Pin Selectable Differential Oscillator with 7 unique reference clock frequencies and configurable output format.

The (...)

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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