|
Analog Bandgap References |
Yes |
Yes |
|
Analog Trim of Some TMX Devices |
Yes |
|
| ADC |
ADC: ADC Post-Processing Block Limit Compare |
Yes |
Yes |
| ADC |
ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt
Mode) is not Set |
Yes |
Yes |
| ADC |
ADC: DMA Read of Stale Result |
Yes |
Yes |
| ADC |
ADC: Random Conversion Errors |
Yes |
|
| ADC |
ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare
Submodule |
Yes |
|
| ADC |
ADC: 12-Bit Switch Resistance |
Yes |
|
| ADC |
ADC: 12-Bit Input Capacitance When Switching Channel
Groups |
Yes |
|
|
XRS may Toggle During Power
Up |
Yes |
|
| CLB |
CLB: Back-to-Back PUSH or PULL Instructions With More Than One
Active High-Level Controller (HLC) Channel is Not
Supported |
Yes |
Yes |
| USB |
USB: USB DMA Event Triggers are not Supported |
Yes |
Yes |
| VREG |
VREG: VREG Will be Enabled During Power Up Irrespective of
VREGENZ |
Yes |
|
| Flash |
Flash: A Single-Bit ECC Error May Cause Endless Calls to
Single-Bit-Error ISR |
Yes |
Yes |
| Flash |
Flash: Minimum Programming Word Size |
Yes |
Yes |
| ePIE |
ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First
Enabled |
Yes |
|
| eQEP |
eQEP: Position Counter Incorrectly Reset on Direction Change
During Index |
Yes |
Yes |
| eQEP |
eQEP: eQEP Inputs in GPIO Asynchronous Mode |
Yes |
Yes |
| HWBIST |
HWBIST: Avoiding Spurious Interrupts While Using
HWBIST |
Yes |
Yes |
| PLL |
PLL: May Not Lock on the First Lock Attempt |
Yes |
Yes |
| PLL |
PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to
be Effective |
Yes |
Yes |
| SDFM |
SDFM: Data Filter Output Does Not Saturate at Maximum Value
With Sinc3 and OSR = 256 |
Yes |
Yes |
| SDFM |
SDFM: Spurious Data Acknowledge Event When Data Filter is
Configured and Enabled for the First Time |
Yes |
Yes |
| SDFM |
SDFM: Spurious Data Acknowledge Event When Data Filter is
Synchronized Using PWM FILRES Signal |
Yes |
Yes |
| SDFM |
SDFM: Comparator Filter Module may Generate Spurious Over-Value
and Under-Value
Conditions |
Yes |
Yes |
| SDFM |
SDFM: Dynamically Changing Threshold Settings (LLT, HLT),
Filter Type, or COSR Settings Will Trigger Spurious Comparator
Events |
Yes |
Yes |
| SDFM |
SDFM: Dynamically Changing Data Filter Settings (Such as Filter
Type or DOSR) Will Trigger Spurious Data Acknowledge
Events |
Yes |
Yes |
| SDFM |
SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter
Results Under Several Conditions |
Yes |
Yes |
| FPU |
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p
Operation |
Yes |
Yes |
| FPU |
FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32
Instructions |
Yes |
Yes |
| Memory |
Memory: Prefetching Beyond Valid Memory |
Yes |
Yes |
| INTOSC |
INTOSC: VDDOSC Powered Without VDD Can
Cause INTOSC Frequency Drift |
Yes |
Yes |
| Low-Power Modes |
Low-Power Modes: Power Down Flash or Maintain Minimum Device
Activity |
Yes |
Yes |
| I2C |
I2C: SDA and SCL Open-Drain Output Buffer Issue |
Yes |
Yes |
| I2C |
I2C: Target Transmitter Mode, Standard Mode SDA Timings
Limitation |
Yes |
Yes |
| ePWM |
ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the
End of the Blanking Window |
Yes |
Yes |
| ePWM |
ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using
Shadow Load Mode for RED/FED |
Yes |
Yes |
| ePWM |
ePWM: Trip Events Will Not be Filtered by the Blanking Window
for the First 3 Cycles After the Start of a Blanking
Window |
Yes |
Yes |
| SYSTEM |
SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a
System Hang |
Yes |
Yes |
| CMPSS |
CMPSS: COMPxLATCH May Not Clear Properly Under Certain
Conditions |
Yes |
Yes |
| CMPSS |
CMPSS: Ramp Generator May Not Start Under Certain
Conditions |
Yes |
Yes |
| GPIO |
GPIO: Open-Drain Configuration May Drive a Short High
Pulse |
Yes |
Yes |
|
During DCAN FIFO Mode, Received Messages May be Placed Out of
Order in the FIFO Buffer |
Yes |
Yes |
| Boot ROM |
Boot ROM: Calling SCI Bootloader from
Application |
Yes |
Yes |
| Boot ROM |
Boot ROM: Device Will Hang During Boot if X1 Clock Source is
not Present |
Yes |
|