SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 15-23 lists the memory-mapped registers for the EMAC. All register offset addresses not listed in Table 15-23 should be considered as reserved locations and the register contents should not be modified.
For the MAC registers, the offsets are relative to the MAC base address of 0x400EC000.
PHY registers are accessed through the EMACMIIADDR register thus the base address is N/A (not applicable). The Ethernet MAC MII Address (EMACMIIADDR) register is used to access MII Management registers on the external PHY device. The PLA field in the EMACMIIADDR register supports PHY addresses 1 to 31. See Section 15.7 for details of the PHY registers.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0x0 | EMACCFG | Ethernet MAC Configuration | Section 15.6.1 |
0x4 | EMACFRAMEFLTR | Ethernet MAC Frame Filter | Section 15.6.2 |
0x8 | EMACHASHTBLH | Ethernet MAC Hash Table High | Section 15.6.3 |
0xC | EMACHASHTBLL | Ethernet MAC Hash Table Low | Section 15.6.4 |
0x10 | EMACMIIADDR | Ethernet MAC MII Address | Section 15.6.5 |
0x14 | EMACMIIDATA | Ethernet MAC MII Data Register | Section 15.6.6 |
0x18 | EMACFLOWCTL | Ethernet MAC Flow Control | Section 15.6.7 |
0x1C | EMACVLANTG | Ethernet MAC VLAN Tag | Section 15.6.8 |
0x24 | EMACSTATUS | Ethernet MAC Status | Section 15.6.9 |
0x28 | EMACRWUFF | Ethernet MAC Remote Wake-Up Frame Filter | Section 15.6.10 |
0x2C | EMACPMTCTLSTAT | Ethernet MAC PMT Control and Status | Section 15.6.11 |
0x30 | EMACLPICTLSTAT | LPI Control and Status | Section 15.6.12 |
0x34 | EMACLPITIMERCTRL | LPI Timers Control | Section 15.6.13 |
0x38 | EMACRIS | Ethernet MAC Raw Interrupt Status | Section 15.6.14 |
0x3C | EMACIM | Ethernet MAC Interrupt Mask | Section 15.6.15 |
0x40 | EMACADDR0H | Ethernet MAC Address 0 High | Section 15.6.16 |
0x44 | EMACADDR0L | Ethernet MAC Address 0 Low Register | Section 15.6.17 |
0x48 | EMACADDR1H | Ethernet MAC Address 1 High | Section 15.6.18 |
0x4C | EMACADDR1L | Ethernet MAC Address 1 Low | Section 15.6.19 |
0x50 | EMACADDR2H | Ethernet MAC Address 2 High | Section 15.6.20 |
0x54 | EMACADDR2L | Ethernet MAC Address 2 Low | Section 15.6.21 |
0x58 | EMACADDR3H | Ethernet MAC Address 3 High | Section 15.6.22 |
0x5C | EMACADDR3L | Ethernet MAC Address 3 Low | Section 15.6.23 |
0xDC | EMACWDOGTO | Ethernet MAC Watchdog Time-out | Section 15.6.24 |
0x100 | EMACMMCCTRL | Ethernet MAC MMC Control | Section 15.6.25 |
0x104 | EMACMMCRXRIS | Ethernet MAC MMC Receive Raw Interrupt Status | Section 15.6.26 |
0x108 | EMACMMCTXRIS | Ethernet MAC MMC Transmit Raw Interrupt Status | Section 15.6.27 |
0x10C | EMACMMCRXIM | Ethernet MAC MMC Receive Interrupt Mask | Section 15.6.28 |
0x110 | EMACMMCTXIM | Ethernet MAC MMC Transmit Interrupt Mask | Section 15.6.29 |
0x118 | EMACTXCNTGB | Ethernet MAC Transmit Frame Count for Good and Bad Frames | Section 15.6.30 |
0x14C | EMACTXCNTSCOL | Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision | Section 15.6.31 |
0x150 | EMACTXCNTMCOL | Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions | Section 15.6.32 |
0x164 | EMACTXOCTCNTG | Ethernet MAC Transmit Octet Count Good | Section 15.6.33 |
0x180 | EMACRXCNTGB | Ethernet MAC Receive Frame Count for Good and Bad Frames | Section 15.6.34 |
0x194 | EMACRXCNTCRCERR | Ethernet MAC Receive Frame Count for CRC Error Frames | Section 15.6.35 |
0x198 | EMACRXCNTALGNERR | Ethernet MAC Receive Frame Count for Alignment Error Frames | Section 15.6.36 |
0x1C4 | EMACRXCNTGUNI | Ethernet MAC Receive Frame Count for Good Unicast Frames | Section 15.6.37 |
0x584 | EMACVLNINCREP | Ethernet MAC VLAN Tag Inclusion or Replacement | Section 15.6.38 |
0x588 | EMACVLANHASH | Ethernet MAC VLAN Hash Table | Section 15.6.39 |
0x700 | EMACTIMSTCTRL | Ethernet MAC Timestamp Control | Section 15.6.40 |
0x704 | EMACSUBSECINC | Ethernet MAC Sub-Second Increment | Section 15.6.41 |
0x708 | EMACTIMSEC | Ethernet MAC System Time - Seconds | Section 15.6.42 |
0x70C | EMACTIMNANO | Ethernet MAC System Time - Nanoseconds | Section 15.6.43 |
0x710 | EMACTIMSECU | Ethernet MAC System Time - Seconds Update | Section 15.6.44 |
0x714 | EMACTIMNANOU | Ethernet MAC System Time - Nanoseconds Update | Section 15.6.45 |
0x718 | EMACTIMADD | Ethernet MAC Timestamp Addend | Section 15.6.46 |
0x71C | EMACTARGSEC | Ethernet MAC Target Time Seconds | Section 15.6.47 |
0x720 | EMACTARGNANO | Ethernet MAC Target Time Nanoseconds | Section 15.6.48 |
0x724 | EMACHWORDSEC | Ethernet MAC System Time-Higher Word Seconds | Section 15.6.49 |
0x728 | EMACTIMSTAT | Ethernet MAC Timestamp Status | Section 15.6.50 |
0x72C | EMACPPSCTRL | Ethernet MAC PPS Control | Section 15.6.51 |
0x760 | EMACPPS0INTVL | Ethernet MAC PPS0 Interval | Section 15.6.52 |
0x764 | EMACPPS0WIDTH | Ethernet MAC PPS0 Width | Section 15.6.53 |
0xC00 | EMACDMABUSMOD | Ethernet MAC DMA Bus Mode | Section 15.6.54 |
0xC04 | EMACTXPOLLD | Ethernet MAC Transmit Poll Demand | Section 15.6.55 |
0xC08 | EMACRXPOLLD | Ethernet MAC Receive Poll Demand | Section 15.6.56 |
0xC0C | EMACRXDLADDR | Ethernet MAC Receive Descriptor List Address | Section 15.6.57 |
0xC10 | EMACTXDLADDR | Ethernet MAC Transmit Descriptor List Address | Section 15.6.58 |
0xC14 | EMACDMARIS | Ethernet MAC DMA Interrupt Status | Section 15.6.59 |
0xC18 | EMACDMAOPMODE | Ethernet MAC DMA Operation Mode | Section 15.6.60 |
0xC1C | EMACDMAIM | Ethernet MAC DMA Interrupt Mask Register | Section 15.6.61 |
0xC20 | EMACMFBOC | Ethernet MAC Missed Frame and Buffer Overflow Counter | Section 15.6.62 |
0xC24 | EMACRXINTWDT | Ethernet MAC Receive Interrupt Watchdog Timer | Section 15.6.63 |
0xC48 | EMACHOSTXDESC | Ethernet MAC Current Host Transmit Descriptor | Section 15.6.64 |
0xC4C | EMACHOSRXDESC | Ethernet MAC Current Host Receive Descriptor | Section 15.6.65 |
0xC50 | EMACHOSTXBA | Ethernet MAC Current Host Transmit Buffer Address | Section 15.6.66 |
0xC54 | EMACHOSRXBA | Ethernet MAC Current Host Receive Buffer Address | Section 15.6.67 |
0xFC0 | EMACPP | Ethernet MAC Peripheral Property Register | Section 15.6.68 |
0xFC4 | EMACPC | Ethernet MAC Peripheral Configuration Register | Section 15.6.69 |
0xFC8 | EMACCC | Ethernet MAC Clock Configuration Register | Section 15.6.70 |
0xFD0 | EPHYRIS | Ethernet PHY Raw Interrupt Status | Section 15.6.71 |
0xFD4 | EPHYIM | Ethernet PHY Interrupt Mask | Section 15.6.72 |
0xFD8 | EPHYMISC | Ethernet PHY Masked Interrupt Status and Clear | Section 15.6.73 |
Complex bit access types are encoded to fit into small table cells. Table 15-24 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1C | 1C
W |
1 to clear
Write |
Reset or Default Value | ||
-n | Value after reset or the default value |